240pin DDR2 VLP Registerd DIMMs based on 1Gb C version
This Hynix DDR2 VLP(Very Low Profile) registered Dual In-Line Memory Module (DIMM) series consists of 1Gb C ver-
sion DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb C ver-
sion based VLP Registered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of
industry standard. It is suitable for easy interchange and addition.
ORDERING INFORMATION
Part Name
HYMP112P72CP8L-C4/Y5/S6
HYMP125P72CP4L-C4/Y5/S6
HYMP351P72CMP4L-C4/Y5/S6
HYMP41GP72CNP4L-C4/Y5
Density
1GB
2GB
4GB
8GB
Org.
128Mbx72
256Mbx72
512Mbx72
1Gbx72
Component Configuration
128Mbx8(HY5PS1G821CFP)*9
256Mbx4(HY5PS1G421CFP)*18
512Mbx4(HY5PS2G421CMP)*18
1Gbx4(HY5PS4G421CNP)*18
Ranks
1
1
2
4
Parity
Support
O
O
O
O
Note:
1. “P” of part number[12th digit] stands for Lead free products.
SPEED GRADE & KEY PARAMETERS
C4 (DDR2-533)
Speed@CL3
Speed@CL4
Speed@CL5
Speed@CL6
CL-tRCD-tRP
400
533
-
-
4-4-4
Y5 (DDR2-667)
400
533
667
-
5-5-5
S6 (DDR2-800)
-
400
533
800
6-6-6
Unit
Mbps
Mbps
Mbps
Mbps
tCK
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / May. 2008
1
1
240pin DDR2 VLP Registered DIMMs
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
JEDEC standard 1.8V +/- 0.1V Power Supply
V
DDQ
: 1.8V +/- 0.1V
All inputs and outputs are compatible with SSTL_1.8 interface
4 Bank architecture
Posted CAS
Programmable CAS Latency 3 , 4 , 5
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
Fully differential clock operations (CK & CK)
Programmable Burst Length 4 / 8 with both sequential and interleave mode
Average Auto Refresh Period 7.8us under T
CASE
85℃, 3.9us at 85℃ < T
CASE
≤
95
℃
High Temperature Self-Refresh Entry enablble features
PASR(Partial Array Self- Refresh)
8192 refresh cycles / 64ms
Serial presence detect with EEPROM
DDR2 SDRAM Package: 60ball FBGA
133.35 x 18.29 mm form factor
Lead-free Products are RoHS compliant
ADDRESS TABLE
Density
1GB
2GB
4GB
8GB
Organization Ranks
128Mb x 72
256Mb x 72
512Mb x 72
1Gb x 72
1
1
2
4
SDRAMs
128Mb x 8
256Mb x 4
256Mb x 4
256Mb x 4
# of
DRAMs
9
18
36
72
# of row/bank/column Address
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
Refresh
Method
8K / 64ms
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64ms
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64m
14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 8K / 64m
Rev. 0.2 / May. 2008
1
240pin DDR2 VLP Registered DIMMs
Input/Output Functional Description
Symbol
CK0
CK0
CKE[1:0]
S[1:0]
ODT[1:0]
RAS, CAS, WE
Vref
V
DDQ
BA[1:0]
Type
IN
IN
IN
IN
IN
IN
Supply
Supply
IN
-
Polarity
Positive
Edge
Pin Description
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Negative
Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Edge
Active
High
Active
Low
Active
High
Active
Low
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
Enables the associated DDR2 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1
On-Die Termination signals.
When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define
the command being entered.
Reference voltage for SSTL18 inputs
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all
current DDR2 unbuffered DIMM designs, V
DDQ
shares the same power plane as V
DD
pins.
Selects which DDR2 SDRAM internal bank of four is activated.
During a Bank Activate command cycle, Address input defines the row address(RA0~RA13)
During a Read or Write command cycle, Address input defines the column address when sam-
pled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column
address, AP is used to invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged.
If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in con-
junction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre-
charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define
which bank to precharge.
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High coin-
cident with that input data during a write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
Power and ground for the DDR2 SDRAM input buffers, and core logic. V
DD
and V
DDQ
pins are
tied to V
DD
/V
DDQ
planes on these modules.
Positive
Edge
Positive line of the differential data strobe for input and output data
A[9:0],
A10/AP
A[13:11]
IN
-
DQ[63:0],
CB[7:0]
DM[8:0]
V
DD
,V
SS
DQS[17:0]
DQS[17:0]
SA[2:0]
SDA
SCL
VDDSPD
RESET
Par_In
Err_Out
TEST
IN
IN
Supply
I/O
I/O
IN
I/O
IN
Supply
IN
IN
OUT
-
Active
High
Negative
Negative line of the differential data strobe for input and output data
Edge
-
-
-
These signals are tied at the system planar to either V
SS
or V
DDSPD
to configure the serial SPD
EEPROM address range.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may
be connected from the SDA bus line to V
DDSPD
on the system planar to act as a pull up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from SCL to V
DDSPD
to act as a pull up on the system board.
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane.
EEPROM supply is operable from 1.7V to 3.6V.
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When
low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will
be set to low level (the PLL will remain synchronized with the input clock)
Parity bit for the Address and Control bus(“1”. Odd, “0”.Even)
Parity error found in the Address and Control bus
Used by memory bus analysis tools(unused on memory DIMMs)
Rev. 0.2 / May. 2008
1
240pin DDR2 VLP Registered DIMMs
PIN DESCRIPTION
Pin
CK0
CK0
Pin Description
Clock Input,positive line
Clock input,negative line
Pin
ODT[1:0]
VDDQ
Pin Description
On Die Termination Inputs
DQs Power Supply
CKE0~CKE1 Clock Enable Input
RAS
CAS
WE
S0,S1
A0~A9,
A11~A13
A10/AP
BA0,BA1
SCL
SDA
SA0~SA2
Par_In
Err_Out
RESET
CB0~CB7
Row Address Strobe
Column Address Strobe
Write Enable
Chip Select Input
Address input
Address input/Autoprecharge
SDRAM Bank Address
Serial Presence Detect(SPD) Clock Input
SPD Data Input/Output
E
2
PROM Address Inputs
Parity bit for the Address and Control bus
Parity error found on the Address
Reset Enable
Data
Check bit
Inputs/Outputs
DQ0~DQ63 Data Input/Output
CB0~CB7
DQS(0~8)
DQS(0~8)
Data check bits Input/Output
Data strobes
Data strobes,negative line
DM(0~8),
Data Maskes/Data strobes
DQS(9~17)
DQS(9~17) Data strobes,negative line
RFU
NC
TEST
VDD
VDDQ
VSS
VREF
VDDSPD
Reserved for Future Use
No Connect
Memory bus test tool
(Not Connected and Not Usable on DIMMs)
Core Power
I/O Power
Ground
Input/Output Reference
SPD Power
PIN LOCATION
Front Side
1 pin
64 pin
65 pin
120 pin
121 pin
Banck Side
184 pin
185 pin
240 pin
Rev. 0.2 / May. 2008
Analog electronics
京公网安备 11010802033920号
EEWORLD
