Freescale Semiconductor
Technical Data
MMA52xxWR2
Rev 0, 02/2010
PSI5 Inertial Sensor
The MMA52wwWR2 family of devices are AKLV27 and PSI5 Version 1.3
compatible overdamped X-axis satellite accelerometers.
Features
±60g to ±480g Full-Scale Range
Selectable 400 Hz, 3 Pole, or 4 pole Low Pass Filter
Single Pole High Pass Filter with Fast Start-Up & Output Rate Limiting
PSI5 Version 1.3 Compatible
– PSI5-P10P-500/3L Compatible
– Programmable Time Slots with 0.5
μs
Resolution
– Selectable Baud Rate: 125 kBaud or 190.5 kBaud
– Selectable Data Length: 8 or 10 bits
– Selectable Error Detection: Even Parity, or 3-bit CRC
– Optional Daisy Chain with External Low Side Switch
– Two-Wire Programming Mode
• 16
μs
Internal Sample Rate, with Interpolation to 1
μs
• Pb-Free 16-Pin QFN, 6 x 6 Package
• Qualified AECQ100, Revision G, Grade 1 (-40°C to +125°C)
Typical Applications
• Airbag Front and Side Crash Detection
V
SSA
MMA52xxWR2
•
•
•
•
PSI5 INERTIAL SENSOR
Bottom View
16-PIN QFN
CASE 2089-01
Top View
BUS_SW
TEST
16 15 14 13
ORDERING INFORMATION
Device
MMA5206W
MMA5206WR2
MMA5206KW
MMA5206KWR2
MMA5212W
MMA5212WR2
MMA5212KW
MMA5212KWR2
MMA5224W
MMA5224WR2
MMA5224KW
MMA5224KWR2
MMA5248W
MMA5248WR2
MMA5248KW
MMA5248KWR2
Axis
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Temperature
Range
60g
60g
60g
60g
120g
120g
120g
120g
240g
240g
240g
240g
480g
480g
480g
480g
Package
2089-01
2089-01
2089-01
2089-01
2089-01
2089-01
2089-01
2089-01
2089-01
2089-01
2089-01
2089-01
2089-01
2089-01
2089-01
2089-01
Shipping
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
V
CC
1
V
SS
2
I
DATA
3
V
SS
4
V
BUF
12 V
SSA
11 V
REGA
10 CS
9 V
REG
8
D
IN
17
5
PCM
6
SLCK
7
D
OUT
PIN CONNECTIONS
”K” suffix indicates device manufactured with an alternate silicon sourcing.
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2010. All rights reserved.
VV
BUF
V
BUF
V
REG
V
REGA
C4
C5
C6
V
CC
I
DATA
R1
R2
C2
C3
C1
V
CE
MMA52xx
V
SSA
V
SS
R3
CS
SCLK
DO
V
SS
Note: Pin names and references
may differ from PSI5 V1.3
pin names and references
DI
PCM
BUS_SW
Optional for
Daisy Chain
M1
V
SS_OUT
Figure 1. Application Diagram
External Component Recommendations
Ref Des
C1
C3
C2
C4, C5, C6
R1
R2
R3
M1
Type
Ceramic
Ceramic
Ceramic
Ceramic
General Purpose
General Purpose
General Purpose
N-Channel MOSFET
Description
2.2 nF, 10%, 50 V minimum, X7R
470 pF, 10%, 50 V minimum, X7R
15 nF, 10%, 50 V minimum, X7R
1 mF, 10%, 10 V minimum, X7R
82
Ω,
5%, 200 PPM
27
Ω,
5%, 200 PPM
20 kΩ, 5%, 200 PPM
—
Purpose
V
CC
Power Supply Decoupling and Signal Damping
I
DATA
Filtering and Signal Damping
V
CC
Power Supply Decoupling
Voltage Regulator Output Capacitor(s)
V
CC
Filtering and Signal Damping
I
DATA
Filtering and Signal Damping
Gate Resistor for External Low Side Daisy Chain FET
Low Side Daisy Chain Transistor
Device Orientation
xxxxxxx
xxxxxxx
X: 0 g
MMA52xxWR
Preliminary
2
Sensors
Freescale Semiconductor
xxxxxxx
xxxxxxx
X: +1 g
Figure 2. Device Orientation Diagram
xxxxxxx
xxxxxxx
X: 0 g
xxxxxxx
xxxxxxx
X: -1 g
X: 0 g
X: 0 g
EARTH GROUND
Internal Block Diagram
V
CC
Buffer
Voltage
Regulator
Reference
Voltage
V
BUF
Digital
Voltage
Regulator
Analog
Voltage
Regulator
V
BUF
V
REG
V
REG
V
REF
V
REGA
V
BUF
V
REGA
V
SSA
CS
SCLK
D
IN
D
OUT
Control
Logic
SPI
Low Voltage
Detection
Sync Pulse
Detection
Programming
Interface
V
CC
OTP
Array
I
DATA
Serial
Encoder
V
SS
Daisy Chain
Switch Driver
BUS_SW
V
REG
Self-Test
Interface
Control
In
Status
Out
DSP
ΣΔ
Converter
V
REGA
g-cell
V
REG
Offset
Monitor
HPF
PCM
Encoder
PCM
SINC Filter
IIR
LPF
Compensation
Figure 3. Block Diagram
MMA52xxWR
Sensors
Freescale Semiconductor
Preliminary
3
1
PIN CONNECTIONS
BUS_SW
TEST
V
BUF
12 V
SSA
11 V
REGA
10 CS
9 V
REG
5
PCM
6
SLCK
7
D
OUT
8
D
IN
Definition
This pin is connected to the PSI5 power and data line through a resistor and supplies power to the device. An external capac-
itor must be connected between this pin and V
SS
. Reference
Figure 1.
This pin is the power supply return node for the digital circuitry.
This pin is connected to the PSI5 power and data line through a resistor and modulates the response current for PSI5 com-
munication. Reference
Figure 1.
This pin is the power supply return node for the digital circuitry.
This pin provides a 4 MHz PCM signal proportional to the acceleration data for test purposes. The output can be enabled via
OTP. Reference
Section 3.5.3.7.
If unused, this pin must be left unconnected.
This input pin provides the serial clock to the SPI port for test purposes. An internal pull-down device is connected to this pin.
This pin must be grounded or left unconnected in the application.
This pin functions as the serial data output from the SPI port for test purposes. This pin must be left unconnected in the appli-
cation.
This pin functions as the serial data input to the SPI port for test purposes. An internal pull-down device is connected to this
pin. This pin must be grounded or left unconnected in the application.
This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be connected between
this pin and V
SS
. Reference
Figure 1.
This input pin provides the chip select to the SPI port for test purposes. An internal pull-up device is connected to this pin.This
pin must be left unconnected in the application.
This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be connected between
this pin and V
SSA
. Reference
Figure 1.
This pin is the power supply return node for the analog circuitry.
This pin is connected to a buffer regulator for the internal circuitry. The buffer regulator supplies both the analog (V
REGA
) and
digital (V
REG
) supplies to provide immunity from EMC and supply dropouts on V
CC
. An external capacitor must be connected
between this pin and V
SS
. Reference
Figure 1.
This pin is must be grounded or left unconnected in the application.
This pin is the drive for a low side daisy chain switch. When daisy chain mode is enabled, this pin is connected to the gate of
an n-channel FET which connects V
SS
to V
SS_OUT.
Reference
Figure 1.
If unused, this pin must be left unconnected.
This pin is the power supply return node for the analog circuitry.
This pin is the die attach flag, and is internally connected to VSS. Reference
Section 7
for die attach pad connection details.
16 15 14 13
V
CC
1
V
SS
2
I
DATA
3
V
SS
4
17
Figure 4. Top View, 16-Pin QFN Package
Table 1. Pin Description
Pin
1
2
3
4
5
Pin
Name
V
CC
V
SS
I
DATA
V
SS
PCM
Formal Name
Supply
Digital GND
Response
Current
Digital GND
PCM
Output
SPI Clock
6
SCLK
7
DOUT
SPI Data Out
8
DIN
SPI Data In
Digital
Supply
Chip Select
Analog
Supply
Analog GND
Power
Supply
Test Pin
Bus Switch
Gate Drive
Analog GND
Die Attach Pad
9
V
REG
CS
10
11
12
V
REGA
VSSA
13
V
BUF
TEST
BUS_SW
VSSA
PAD
14
15
16
17
MMA52xxWR
Preliminary
4
Sensors
Freescale Semiconductor
V
SSA
2
2.1
#
1
2
3
4
5
6
7
8
ELECTRICAL CHARACTERISTICS
Maximum Ratings
Rating
Supply Voltage (V
CC
, I
DATA
)
Reverse Current
≤
160 mA, t
≤
80 ms
Continuous
Transient (< 10
μs)
V
BUF,
Test, BUS_SW
V
REG
, V
REGA
,
SCLK, CS, D
IN
, D
OUT
, PCM
Powered Shock (six sides, 0.5 ms duration)
Unpowered Shock (six sides, 0.5 ms duration)
Drop Shock (to concrete, tile or steel surface, 10 drops, any orientation)
Electrostatic Discharge (per AEC-Q100)
External Pins (V
CC
, I
DATA
, V
SS
, V
SSA
), HBM (100 pF, 1.5 kΩ)
HBM (100 pF, 1.5 kΩ)
CDM (R = 0
Ω)
MM (200 pF, 0
Ω)
Temperature Range
Storage
Junction
Thermal Resistance
g
pms
g
shock
h
DROP
V
ESD
V
ESD
V
ESD
V
ESD
T
stg
T
J
θ
JC
Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it.
Symbol
V
CC_REV
V
CC_MAX
V
CC_TRANS
Value
-0.7
+20.0
+25.0
-0.3 to +4.2
-0.3 to +3.0
±2000
±2500
1.2
±4000
±2000
±1500
±200
-40 to +125
-40 to +150
2.5
Unit
V
V
V
V
V
g
g
m
(3)
(3)
(9)
(3)
(3)
(3)
(3)
(5)
9
10
11
12
V
V
V
V
(5)
(5)
(5)
(5)
13
14
15
°C
°C
°C/W
(3)
(9)
(9,14)
2.2
#
16
17
18
Operating Range
Characteristic
Supply Voltage
Programming Voltage (I
DATA
≤
85 mA)
Applied to I
DATA,
V
CC
Operating Temperature Range
V
L
≤
(V
CC
- V
SS
)
≤
V
H
, T
L
≤
T
A
≤
T
H
,
ΔT ≤
25 K/min, unless otherwise specified
Symbol
V
CC
V
CC_UV
VPP
Min
V
L
4.2
V
VCC_UV_F
14.0
T
L
-40
Typ
—
—
Max
V
H
17.0
V
L
—
T
H
+125
Units
V
V
(1)
(9)
—
V
(3)
19
T
A
—
C
(1)
MMA52xxWR
Sensors
Freescale Semiconductor
Preliminary
5
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