MPC8323ZQADDCA datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > semiconductor> The embedded processor and controller> MPC8323ZQADDCA

MPC8323ZQADDCA: Description32-BIT, 266 MHz, RISC PROCESSOR, PBGA516; Categorysemiconductor The embedded processor and controller; File Size991KB，82 Pages; ManufacturerFREESCALE (NXP)

Download Datasheet Parametric Compare View All

MPC8323ZQADDCA Overview

32-BIT, 266 MHz, RISC PROCESSOR, PBGA516

MPC8323ZQADDCA Parametric

Parameter Name	Attribute value
External data bus width	0.0
Number of terminals	516
Line speed	266 MHz
Processing package description	27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, PLASTIC, PBGA-516
state	EOL
microprocessor_microcontroller_peripheral_ic_type	MICROPROCESSOR, RISC
Address bus width	0.0
Number of digits	32
boundary scan	YES
clock_frequency_max	66.67 MHz
form	FLOATING POINT
Integrated cache	YES
jesd_30_code	S-PBGA-B516
jesd_609_code	e0
low power mode	YES
Packaging Materials	PLASTIC/EPOXY
ckage_code	BGA
packaging shape	SQUARE
Package Size	GRID ARRAY
qualification_status	COMMERCIAL
seated_height_max	2.55 mm
Rated supply voltage	1 V
Minimum supply voltage	0.9500 V
Maximum supply voltage	1.05 V
surface mount	YES
terminal coating	TIN LEAD SILVER
Terminal form	BALL
Terminal spacing	1 mm
Terminal location	BOTTOM
length	27 mm
width	27 mm

Preview

Download Datasheet

View All

Freescale Semiconductor

Technical Data

Document Number: MPC8323EEC

Rev. 4, 09/2010

MPC8323E

PowerQUICC II Pro Integrated

Communications Processor

Family Hardware Specifications

This document provides an overview of the MPC8323E

PowerQUICC II Pro processor features. The MPC8323E is a

cost-effective, highly integrated communications processor

that addresses the requirements of several networking

applications, including ADSL SOHO and residential

gateways, modem/routers, industrial control, and test and

measurement applications. The MPC8323E extends current

PowerQUICC offerings, adding higher CPU performance,

additional functionality, and faster interfaces, while

addressing the requirements related to time-to-market, price,

power consumption, and board real estate. This document

describes the MPC8323E, and unless otherwise noted, the

information also applies to the MPC8323, MPC8321E, and

MPC8321.

To locate published errata or updates for this document, refer

to the MPC8323E product summary page on our website

listed on the back cover of this document or contact your

local Freescale sales office.

10.

11.

12.

13.

14.

15.

16.

17.

18.

19.

20.

21.

22.

23.

24.

25.

26.

Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 9

Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 11

DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . 13

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Ethernet and MII Management . . . . . . . . . . . . . . . . . 19

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

UTOPIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

HDLC, BISYNC, Transparent, and Synchronous

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 49

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

System Design Information . . . . . . . . . . . . . . . . . . . 76

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 79

Document Revision History . . . . . . . . . . . . . . . . . . . 80

Overview

NOTE

The QUICC Engine block can also support a UTOPIA level 2 capable of

supporting 31 multi-PHY (MPC8323E- and MPC8323-specific).

The MPC8323E security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be offloaded

from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES,

3DES, AES, SHA-1, and MD-5 algorithms.

In summary, the MPC8323E family provides users with a highly integrated, fully programmable

communications processor. This helps ensure that a low-cost system solution can be quickly developed

and offers flexibility to accommodate new standards and evolving system requirements.

1.1

MPC8323E Features

Major features of the MPC8323E are as follows:

• High-performance, low-power, and cost-effective single-chip data-plane/control-plane solution for

ATM or IP/Ethernet packet processing (or both).

• MPC8323E QUICC Engine block offers a future-proof solution for next generation designs by

supporting programmable protocol termination and network interface termination to meet evolving

protocol standards.

• Single platform architecture supports the convergence of IP packet networks and ATM networks.

• DDR1/DDR2 memory controller—one 32-bit interface at up to 266 MHz supporting both DDR1

and DDR2.

• An e300c2 core built on Power Architecture technology with 16-Kbyte instruction and data caches,

and dual integer units.

• Peripheral interfaces such as 32-bit PCI (2.2) interface up to 66-MHz operation, 16-bit local bus

interface up to 66-MHz operation, and USB 2.0 (full-/low-speed).

• Security engine provides acceleration for control and data plane security protocols.

• High degree of software compatibility with previous-generation PowerQUICC processor-based

designs for backward compatibility and easier software migration.

1.1.1

Protocols

The protocols are as follows:

• ATM SAR up to 155 Mbps (OC-3) full duplex, with ATM traffic shaping (ATF TM4.1)

• Support for ATM AAL1 structured and unstructured circuit emulation service (CES 2.0)

• Support for IMA and ATM transmission convergence sub-layer

• ATM OAM handling features compatible with ITU-T I.610

• IP termination support for IPv4 and IPv6 packets including TOS, TTL, and header checksum

processing

• Extensive support for ATM statistics and Ethernet RMON/MIB statistics

• Support for 64 channels of HDLC/transparent

MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4

Freescale Semiconductor

Overview

1.1.2

Serial Interfaces

The MPC8323E serial interfaces are as follows:

• Support for one UL2 interface with 31 multi-PHY addresses (MPC8323E and MPC8323 only)

• Support for up to three 10/100 Mbps Ethernet interfaces using MII or RMII

• Support for up to four T1/E1/J1/E3 or DS-3 serial interfaces (TDM)

• Support for dual UART and SPI interfaces and a single I

C interface

1.2

QUICC Engine Block

The QUICC Engine block is a versatile communications complex that integrates several communications

peripheral controllers. It provides on-chip system design for a variety of applications, particularly in

communications and networking systems. The QUICC Engine block has the following features:

• One 32-bit RISC controller for flexible support of the communications peripherals

• Serial DMA channel for receive and transmit on all serial channels

• Five universal communication controllers (UCCs) supporting the following protocols and

interfaces (not all of them simultaneously):

— 10/100 Mbps Ethernet/IEEE 802.3® standard

— IP support for IPv4 and IPv6 packets including TOS, TTL, and header checksum processing

— ATM protocol through UTOPIA interface (note that the MPC8321 and MPC8321E do not

support the UTOPIA interface)

— HDLC /transparent up to 70-Mbps full-duplex

— HDLC bus up to 10 Mbps

— Asynchronous HDLC

— UART

— BISYNC up to 2 Mbps

— QUICC multi-channel controller (QMC) for 64 TDM channels

• One UTOPIA interface (UPC1) supporting 31 multi-PHYs (MPC8323E- and MPC8323-specific)

• Two serial peripheral interfaces (SPI). SPI2 is dedicated to Ethernet PHY management.

• Four TDM interfaces

• Thirteen independent baud rate generators and 19 input clock pins for supplying clocks to UCC

serial channels

• Four independent 16-bit timers that can be interconnected as two 32-bit timers

The UCCs are similar to the PowerQUICC II peripherals: SCC (BISYNC, UART, and HDLC bus) and

FCC (fast Ethernet, HDLC, transparent, and ATM).

MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4

Freescale Semiconductor

MPC8323ZQADDCA Related Products

	MPC8323ZQADDCA	MPC8323CZQADDCA	MPC8323ECZQADDCA	MPC8323EZQADDCA	MPC8323ZQAFDCA
Description	32-BIT, 266 MHz, RISC PROCESSOR, PBGA516	RISC PROCESSOR	RISC PROCESSOR	RISC PROCESSOR	RISC PROCESSOR
state	EOL	EOL	EOL	EOL	EOL
microprocessor_microcontroller_peripheral_ic_type	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC
jesd_609_code	e0	e0	e0	e0	e0
terminal coating	TIN LEAD SILVER	TIN LEAD	TIN LEAD	TIN LEAD	TIN LEAD
moisture_sensitivity_level	-	3	3	3	3
eak_reflow_temperature__cel_	-	260	260	260	260
ime_peak_reflow_temperature_max__s_	-	40	40	40	40

Recommended Resources

Car turning flasher circuit three

two-wire tone encoder

TMP01 type sensor circuit for setting temperature control

Internal circuit diagram of STRD1816

555 single power supply converted into positive and negative voltage regulator circuit

Capacitor step-down driver LED circuit 2

【TI荐课】#Amplifier Protection Series#: //training.eeworld.com.cn/TI/show/course/5648...; 珺珺 TI Technology Forum

A series of problems encountered in the STM32 RTC experiment: According to the RTC routine on the Jinniu development board, I burned the program to the Jinniu development board with STM32F107VCT6, and used the computer's built-in hyperterminal to receive it. I f...; 霜天 stm32/stm8

NIOS Processor Development Reference Manual: altera introduces the official documentation of NIOS processors.Introduce the structure and programming of the processor,It also introduces how to propose the detailed structure of NIOS kernel and NIO...; wstt FPGA/CPLD

Infrared remote control receiving circuit (T9149A): Infrared remote control receiving circuit (T9149A)...; zzzzer16 Analog electronics

Can the CAMERA interface of 2440 directly receive data in Bayer format?: I would like to ask you: Can the CAMERA interface of 2440 directly receive data in Bayer format?...; eq2001k Embedded System

DS-5 software online debugging makefile problem: The bin file of the bare-metal application compiled by DS-5 software can run normally when downloaded to the development board QSPI, but if you want to debug the application online on the host, you ne...; 包玉刚 FPGA/CPLD

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components