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LTC2654IUF-L12PBF

Description
Quad 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference
File Size331KB,24 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
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LTC2654IUF-L12PBF Overview

Quad 16-/12-Bit Rail-to-Rail DACs with 10ppm/°C Max Reference

FEATURES
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LTC2654
Quad 16-/12-Bit Rail-to-Rail
DACs with 10ppm/°C
Max Reference
DESCRIPTION
The LTC
®
2654 is a family of quad 16-/12-bit rail-to-rail
DACs with integrated 10ppm/°C maximum reference . The
DACs have built-in high performance, rail-to-rail, output
buffers and are guaranteed monotonic. The LTC2654-L
has a full-scale output of 2.5V with the integrated refer-
ence and operates from a single 2.7V to 5.5V supply.
The LTC2654-H has a full-scale output of 4.096V with
the integrated reference and operates from a 4.5V to
5.5V supply. Each DAC can also operate with an external
reference, which sets the full-scale output to 2 times the
external reference voltage.
These DACs communicate via a SPI/MICROWIRE™ com-
patible 4-wire serial interface which operates at clock rates
up to 50MHz. The LTC2654 incorporates a power-on reset
circuit that is controlled by the PORSEL pin. If PORSEL
is tied to GND the DACs reset to zero-scale. If PORSEL is
tied to V
CC
, the DACs reset to mid-scale.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. SPI/MICROWIRE is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 5396245, 6891433 and patent pending.
Precision Reference 10ppm/°C Max
Maximum INL Error: ±4LSB at 16-Bits
Low ±2mV (Max) Offset Error
Guaranteed Monotonic Over Temperature
Selectable Internal or External Reference
2.7V to 5.5V Supply Range (LTC2654-L)
Integrated Reference Buffers
Ultralow Crosstalk Between DACs (<3nV•s)
Power-on-Reset to Zero-Scale/Mid-Scale
Asynchronous DAC Update Pin
Tiny 20-Lead 4mm
×
4mm QFN and 16-Lead Narrow
SSOP Packages
APPLICATIONS
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Mobile Communications
Process Control and Industrial Automation
Instrumentation
Automatic Test Equipment
Automotive
BLOCK DIAGRAM
REFCOMP
GND
REFLO
REGISTER
REGISTER
REGISTER
REGISTER
V
OUTA
DAC A
DAC D
V
OUTD
3
2
INL (LSB)
1
0
–1
–2
–3
CONTROL LOGIC
SCK
SDI
LDAC
32-BIT SHIFT REGISTER
CLR
DECODE
POWER-ON
RESET
PORSEL
SDO
–4
128
16384
32768
CODE
49152
65535
2654 TA01b
INTERNAL REFERENCE
REFIN/OUT
V
CC
INL Curve
4
V
CC
= 5V
REGISTER
REGISTER
REGISTER
REGISTER
V
OUTB
DAC B
DAC C
V
OUTC
CS/LD
2654 TA01a
2654f
1

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