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AS7C33256NTD18B-133TQC

Description
3.3V 256K x 8 Pipelined SRAM with NTD
Categorystorage    storage   
File Size419KB,18 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Download Datasheet Parametric View All

AS7C33256NTD18B-133TQC Overview

3.3V 256K x 8 Pipelined SRAM with NTD

AS7C33256NTD18B-133TQC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeQFP
package instructionLQFP, QFP100,.63X.87
Contacts100
Reach Compliance Codeunknow
ECCN code3A991.B.2.A
Maximum access time4 ns
Other featuresPIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)133 MHz
I/O typeCOMMON
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
memory density4718592 bi
Memory IC TypeZBT SRAM
memory width18
Number of functions1
Number of terminals100
word count262144 words
character code256000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX18
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Encapsulate equivalent codeQFP100,.63X.87
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum standby current0.03 A
Minimum standby current3.14 V
Maximum slew rate0.325 mA
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
February 2005
®
AS7C33256NTD18B
3.3V 256K×18 Pipelined SRAM with NTD
TM
Features
• Organization: 262,144 words × 18 bits
• NTD
architecture for efficient bus operation
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.0/3.5/4.0 ns
• Fast OE access time: 3.0/3.5/4.0 ns
• Fully synchronous operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold
Logic block diagram
A[17:0]
18
D
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Address
register
Burst logic
Q
18
CLK
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
LBO
ZZ
DQ [a:b]
18
Write delay
addr. registers
CLK
D
Q
18
Control
logic
CLK
CLK
Write Buffer
256K x 18
SRAM
Array
D
Data
Q
Input
Register
CLK
18
18
18
18
CLK
CEN
CLK
OE
Output
Register
18
OE
DQ [a:b]
Selection Guide
-200
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
5
200
3.0
375
135
30
-166
6
166
3.5
350
120
-133
7.5
133
4
325
110
Units
ns
MHz
ns
mA
mA
mA
30
30
2/8/05;
v.1.5
Alliance Semiconductor
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Copyright © Alliance Semiconductor. All rights reserved.
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