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AS7C33256NTF32A-85TQC

Description
3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD
Categorystorage    storage   
File Size411KB,18 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Download Datasheet Parametric View All

AS7C33256NTF32A-85TQC Overview

3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD

AS7C33256NTF32A-85TQC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codeunknow
ECCN code3A991.B.2.A
Maximum access time8.5 ns
Other featuresFLOW-THROUGH ARCHITECTURE
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
memory density8388608 bi
Memory IC TypeZBT SRAM
memory width32
Number of functions1
Number of terminals100
word count262144 words
character code256000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX32
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
November 2004
®
AS7C33256NTF32A
AS7C33256NTF36A
3.3V 256K×32/36 Flowthrough Synchronous SRAM with NTD
TM
Features
• Organization: 262,144 words × 32 or 36 bits
• NTD
architecture for efficient bus operation
• Fast clock to data access: 7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3 core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• 30 mW typical standby power
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic Block Diagram
A[17:0]
18
D
Address
register
Burst logic
Q
18
CLK
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
D
Q
18
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
CLK
256K x 32/36
SRAM
Array
DQ[a,b,c,d]
32/36
D
Data
Q
Input
Register
CLK
32/36
32/36
32/36
32/36
CLK
CEN
OE
Output
Buffer
32/36
OE
DQ[a,b,c,d]
Selection Guide
-75
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
8.5
7.5
300
120
30
-85
10
8.5
280
110
30
-10
12
10
240
100
30
Units
ns
ns
mA
mA
mA
11/8/04, v. 1.1
Alliance Semiconductor
P. 1 of 18
Copyright © Alliance Semiconductor. All rights reserved.
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