EEWORLDEEWORLDEEWORLD

Part Number

Search

AS7C33256PFS18B-133TQIN

Description
3.3V 256K X 18 pipeline burst synchronous SRAM
Categorystorage    storage   
File Size525KB,19 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Environmental Compliance
Download Datasheet Parametric View All

AS7C33256PFS18B-133TQIN Overview

3.3V 256K X 18 pipeline burst synchronous SRAM

AS7C33256PFS18B-133TQIN Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeQFP
package instructionLQFP, QFP100,.63X.87
Contacts100
Reach Compliance Codeunknow
ECCN code3A991.B.2.A
Maximum access time10 ns
Other featuresFLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)133 MHz
I/O typeCOMMON
JESD-30 codeR-PQFP-G100
JESD-609 codee3
length20 mm
memory density4718592 bi
Memory IC TypeSTANDARD SRAM
memory width18
Number of functions1
Number of terminals100
word count262144 words
character code256000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize256KX18
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Encapsulate equivalent codeQFP100,.63X.87
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)245
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum standby current0.03 A
Minimum standby current3.14 V
Maximum slew rate0.325 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width14 mm
December 2004
®
AS7C33256PFS18B
3.3V 256K
×
18 pipeline burst synchronous SRAM
Features
Organization: 262,144 words × 18 bits
Fast clock speeds to 200 MHz
Fast clock to data access: 3.0/3.5/4.0 ns
Fast OE access time: 3.0/3.5/4.0 ns
Fully synchronous register-to-register operation
Single-cycle deselect
Asynchronous output enable control
Available in 100-pin TQFP package
Individual byte write and global write
Multiple chip enables for easy expansion
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[17:0]
CLK
CS
CLR
Burst logic
18
16
18
18
18
Q
D
Address
CS
register
CLK
256K × 18
Memory
array
18
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
CLK
D
DQa
Q
CLK
D
Byte Write
registers
Byte Write
registers
Enable
register
Q
OE
2
Input
registers
CLK
CE
CLK
ZZ
Output
registers
CLK
Power
down
D
Enable
Q
delay
register
CLK
OE
18
DQ [a,b]
Selection guide
–200
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
5
200
3.0
375
130
30
–166
6
166
3.5
350
100
30
–133
7.5
133
4
325
90
30
Units
ns
MHz
ns
mA
mA
mA
12/10/04; v.1.7
Alliance Semiconductor
P. 1 of 19
Copyright © Alliance Semiconductor. All rights reserved.
Earn points, settle quickly
...
lylhust Embedded System
STM32F 3.0 firmware library core-cm3.C
Why doesn't the STM32F 3.0 firmware library core-cm3.c include core-cm3.h? But core-cm3.c clearly uses the functions declared in core-cm3.h....
anvy178 stm32/stm8
How to use Makefile in wince
For some reason, my ce project needs to be compiled using makefile. But I found that the eVC makefile always makes mistakes. I simply generated an MFC exe project t2, without adding anything, and comp...
xefon Embedded System
Will TIM4 conflict with FSMC after remap in STM32F103VCT6?
After TIM4 remap, its CH1-CH4 are respectively connected to A17, A18, D0, and D1 of FSMC. I only use TIM4_CH1 and do not use A17 and A18 of FSMC. In this way, can TIM4_CH1 output normally? Will it aff...
chinaxu1986 stm32/stm8
[Reliable Example Alliance] 20131231 The problem of malloc/free and heap is essentially (heap) memory management
[i=s]This post was last edited by Xin Xin on 2013-12-31 21:03[/i] I really don't mean to cause a new wave of discussion: [size=4][b] About the use of malloc/free on microcontrollers. [/b][/size] I wro...
辛昕 Programming Basics
About vivi transplantation
I borrowed a board, but I don't have the CD, so I don't have the source code of VIVI. I downloaded the code of VIVI and used DM9000, but my board uses CS8900. I have the driver of 8900 in the director...
bjhualin Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2445  148  271  2910  1010  50  3  6  59  21 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号