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AS7C332MNTF18A-75TQC

Description
3.3V 2M x 18 Flowthrough SRAM with NTD
Categorystorage    storage   
File Size399KB,18 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Download Datasheet Parametric View All

AS7C332MNTF18A-75TQC Overview

3.3V 2M x 18 Flowthrough SRAM with NTD

AS7C332MNTF18A-75TQC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codeunknow
ECCN code3A991.B.2.A
Maximum access time7.5 ns
Other featuresFLOW-THROUGH ARCHITECTURE; LATE WRITE
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
memory density37748736 bi
Memory IC TypeZBT SRAM
memory width18
Number of functions1
Number of terminals100
word count2097152 words
character code2000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize2MX18
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
December 2004
®
AS7C332MNTF18A
3.3V 2M x 18 Flowthrough SRAM with NTD
TM
Features
Organization: 2,097,152 words × 18 bits
NTD
architecture for efficient bus operation
Fast clock to data access: 7.5/8.5/10 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous operation
Flow-through mode
Asynchronous output enable control
Available in 100-pin TQFP package
Byte write enables
Clock enable for operation hold
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Self-timed write cycles
Interleaved or linear burst modes
Snooze mode for standby operation
Logic block diagram
A[19:0]
20
D
Address
register
burst logic
Q
20
CLK
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
LBO
ZZ
CLK
D
Q
20
Write delay
addr. registers
CLK
Control
logic
CLK
Write Buffer
2M x 18
SRAM
array
DQ [a,b]
18
D
Data
Q
input
register
CLK
18
18
18
18
CLK
CEN
OE
Output
buffer
18
OE
DQ [a,b]
Selection guide
-75
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
8.5
7.5
325
140
90
-85
10
8.5
300
130
90
-10
12
10
375
130
90
Units
ns
ns
mA
mA
mA
12/23/04, v 1.2
Alliance Semiconductor
P. 1 of 18
Copyright © Alliance Semiconductor. All rights reserved.
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