HT46R064/065/066/0662/067
Enhanced A/D Type 8-Bit OTP MCU
Technical Document
·
Application Note
-
HA0075E MCU Reset and Oscillator Circuits Application Note
Features
CPU Features
·
Operating voltage:
·
Table read instructions
·
63 powerful instructions
·
Up to 8-level subroutine nesting
·
Bit manipulation instruction
·
Low voltage reset function
·
Wide range of available package types
f
SYS
= 4MHz: 2.2V~5.5V
f
SYS
= 8MHz: 3.0V~5.5V
f
SYS
= 12MHz: 4.5V~5.5V
·
Up to 0.33ms instruction cycle with 12MHz system
clock at V
DD
= 5V
·
Idle/Sleep mode and wake-up functions to reduce
Peripheral Features
·
Up to 42 bidirectional I/O lines
·
Up to 8 channel 12-bit ADC
·
Up to 3 channel 8-bit PWM
·
Software controlled 4-SCOM lines LCD driver with
power consumption
·
Oscillator types:
External high frequency Crystal -- HXT
External RC -- ERC
Internal RC -- HIRC
External low frequency crystal -- LXT
·
Four operational modes: Normal, Slow, Idle, Sleep
·
Fully integrated internal 4MHz, 8MHz and 12MHz
1/2 bias
·
External interrupt input shared with an I/O line
·
Up to three 8-bit programmable Timer/Event
oscillator requires no external components
·
Watchdog Timer function
·
LIRC oscillator function for watchdog timer
·
All instructions executed in one or two instruction
Counter with overflow interrupt and prescaler
·
Time-Base function
·
Programmable Frequency Divider - PFD
cycles
General Description
The Enhanced A/D MCUs are a series of 8-bit high per-
formance, RISC architecture microcontrollers specifi-
cally designed for a wide range of applications. The
usual Holtek microcontroller features of low power con-
sumption, I/O flexibility, timer functions, oscillator op-
tions, power down and wake-up functions, watchdog
timer and low voltage reset, combine to provide devices
with a huge range of functional options while still main-
taining a high level of cost effectiveness. The fully inte-
grated system oscillator HIRC, which requires no
external components and which has three frequency
selections, opens up a huge range of new application
possibilities for these devices, some of which may in-
clude industrial control, consumer products, household
appliances subsystem controllers, etc.
Rev. 1.30
1
January 22, 2013
HT46R064/065/066/0662/067
Pin Assignment
P A 3 /IN T /A N 3
1
2
3
4
5
6
7
8
9
1 0
P A 2 /T C 0 /A N 2
P A 3 /IN T /A N 3
P A 2 /T C 0 /A N 2
P A 1 /P F D /A N 1
P A 0 /A N 0
V S S
P B 0
P B 1
P B 2
8
7
6
5
4
3
2
1
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
P A 4 /P W M 0
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
V D D
P B 5
P B 4
P B 3
P A 1 /P F D /A N 1
P A 0 /A N 0
V S S
P C 0
P C 1
P B 0
P B 1
P B 2
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
P A 4 /P W M 0
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
V D D
P C 3
P C 2
P B 5
P B 4
P B 3
P A 3 /IN T /A N 3
P A 2 /T C 0 /A N 2
P A 1 /P F D /A N 1
P A 0 /A N 0
V S S
P B 0 /S C O M 0
P B 1 /S C O M 1
P B 2 //S C O M 2
8
7
6
5
4
3
2
1
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
P A 4 /P W M 0 /T C 1
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
V D D
P B 5
P B 4
P B 3 /S C O M 3
H T 4 6 R 0 6 4
1 6 D IP -A /N S O P -A
H T 4 6 R 0 6 4
2 0 D IP -A /S O P -A /S S O P -A
H T 4 6 R 0 6 5
1 6 D IP -A /N S O P -A
P A 3 /IN T /A N 3
P A 2 /T C 0 /A N 2
P A 3 /IN T /A N 3
1
2
3
4
5
6
7
8
9
1 0
P A 2 /T C 0 /A N 2
P A 1 /P F D /A N 1
P A 0 /A N 0
V S S
P C 0
P C 1
P B 0 /S C O M 0
P B 1 /S C O M 1
P B 2 //S C O M 2
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
P A 4 /P W M 0 /T C 1
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
V D D
P C 3
P C 2
P B 5
P B 4
P B 3 /S C O M 3
P A 1 /P F D /A N 1
P A 0 /A N 0
V S S
P C 6
P C 7
P C 0
P C 1
P B 0 /S C O M 0
P B 1 /S C O M 1
P B 2 //S C O M 2
9
8
7
6
5
4
3
2
1
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 0
1 1
1 2
1 5
1 4
1 3
P A 4 /P W M 0 /T C 1
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
V D D
P C 5
P C 4
P C 3
P C 2
P B 5
P B 4
P B 3 /S C O M 3
P A 3 /IN T /A N 3
P A 2 /T C 0 /A N 2
P A 1 /P F D /A N 1
P A 0 /A N 0
V S S
P B 0 /S C O M 0
P B 1 /S C O M 1
P B 2 //S C O M 2
8
7
6
5
4
3
2
1
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
P A 4 /P W M 0 /T C 1
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
V D D
P C 3 /P W M 1
P B 4
P B 3 /S C O M 3
H T 4 6 R 0 6 5
2 0 D IP -A /S O P -A /S S O P -A
H T 4 6 R 0 6 5
2 4 S K D IP -A /S O P -A /S S O P -A
H T 4 6 R 0 6 6
1 6 D IP -A /N S O P -A
P A 3 /IN T /A N 3
P A 2 /T C 0 /A N 2
P A 3 /IN T /A N 3
P A 2 /T C 0 /A N 2
P A 3 /IN T /A N 3
1
2
3
4
5
6
7
8
9
1 0
P A 2 /T C 0 /A N 2
P A 1 /P F D /A N 1
P A 0 /A N 0
V S S
P C 0 /A N 4
P C 1 /A N 5
P B 0 /S C O M 0
P B 1 /S C O M 1
P B 2 //S C O M 2
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
P A 4 /P W M 0 /T C 1
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
V D D
P C 3 /P W M 1
P C 2
P B 5 /[IN T ]
P B 4 /[T C 0 ]
P B 3 /S C O M 3 /[P F D ]
P A 1 /P F D /A N 1
P A 0 /A N 0
V S S
P C 6 /A N 6
P C 7 /A N 7
P C 0 /A N 4
P C 1 /A N 5
P B 0 /S C O M 0
P B 1 /S C O M 1
P B 2 //S C O M 2
9
1 0
1 1
1 2
8
7
6
5
4
3
2
1
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
P A 4 /P W M 0 /T C 1
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
V D D
P C 5
P C 4
P C 3 /P W M 1
P C 2
P B 5 /[IN T ]
P B 4 /[T C 0 ]
P B 3 /S C O M 3 /[P F D ]
P A 1 /P F D /A N 1
P A 0 /A N 0
V S S
P C 6 /A N 6
P C 7 /A N 7
P C 0 /A N 4
P C 1 /A N 5
P D 0
P D 1
P B 0 /S C O M 0
P B 1 /S C O M 1
P B 2 //S C O M 2
9
8
7
6
5
4
3
2
1
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 0
1 1
1 2
1 3
1 4
1 9
1 8
1 7
1 6
1 5
P A 4 /P W M 0 /T C 1
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
V D D
P C 5
P C 4
P C 3 /P W M 1
P C 2
P D 3
P D 2
P B 5 /[IN T ]
P B 4 /[T C 0 ]
P B 3 /S C O M 3 /[P F D ]
H T 4 6 R 0 6 6
2 0 D IP -A /S O P -A /S S O P -A
H T 4 6 R 0 6 6
2 4 S K D IP -A /S O P -A /S S O P -A
H T 4 6 R 0 6 6
2 8 S K D IP -A /S O P -A /S S O P -A
Rev. 1.30
3
January 22, 2013
HT46R064/065/066/0662/067
V
P A 7 /R
P A 6 /O S
P A 5 /O S
P A 4 /P W M 0 /T
P A 3 /IN T /A
P A 2 /T C 0 /A
P A 1 /P F D /A
P A 0 /A
V
P C 6 /A
D D
E S
C 1
C 2
C 1
N 3
N 2
N 1
N 0
S S
N 6
4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4
1
2
3
P A 3 /IN T /A
N 3
P A 2 /T C 0 /A
N 2
P A 1 /P F D /A
N 1
P A 0 /A
N 0
4
5
6
7
8
9
P C 5 /X T 1
P C 4 /X T 2
P C 3 /P W M 1
P C 2
P D 7
P D 6
P D 5
P D 4
P D 3
P D 2
P F 1
V S S
P C 6 /A
N 6
P C 7 /A
N 7
P C 0 /A
N 4
P C 1 /A
N 5
P B 0 /S C O M 0
P B 1 /S C O M 1
P B 2 //S C O M 2
3
2
1
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 0
1 1
1 2
1 5
1 4
1 3
P A 4 /P W M 0 /T C 1
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
V D D
P C 5 /X T 1
P C 4 /X T 2
P C 3 /P W M 1
P C 2
P B 5 /[IN T ]
P B 4 /[T C 0 ]
P B 3 /S C O M 3 /[P F D ]
P C 7 /A N
P C 0 /A N
P C 1 /A N
P E
P E
P E
P E
P E
P E
P E
P E
4
5
0
1
2
3
4
5
6
7
7
4
5
6
7
8
9
3 3
3 2
3 1
3 0
H T 4 6 R 0 6 6 2
4 4 L Q F P -A
2 9
2 8
2 7
2 6
2 5
1 0
1 1
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
2 4
2 3
H T 4 6 R 0 6 6 2
2 4 S K D IP -A /S O P -A /S S O P -A
P A 3 /IN T /A N 3
P A 2 /T C 0 /A N 2
P A 1 /P F D /A N 1
P A 0 /A N 0
V S S
P C 6 /A N 6
P C 7 /A N 7
P C 0 /A N 4
P C 1 /A N 5
P D 0
P D 1
P B 0 /S C O M 0
P B 1 /S C O M 1
P B 2 //S C O M 2
9
8
7
6
5
4
3
2
P A 3 /IN T /A
N 3
P A 2 /T C 0 /A
N 2
P A 1 /P F D /A
N 1
P A 0 /A
N 0
V S S
P C 6 /A
N 6
P C 7 /A
N 7
P C 0 /A
N 4
P C 1 /A
N 5
P B 0 /S C O M 0
P B 1 /S C O M 1
P B 2 /S C O M 2
9
8
7
6
5
4
3
2
Note: Bracketed pin names indicate non-default pinout remapping locations.
P F 0
P B 7
P B 6
P B 5
P B 4
P B 3
P B 2
P B 1
P B 0
P D 1
P D 0
H T 4 6 R 0 6 6 2
2 8 S K D IP -A /S O P -A /S S O P -A
H T 4 6 R 0 6 7
2 4 S K D IP -A /S O P -A /S S O P -A
/[IN
/[T C
/S C
/S C
/S C
/S C
T ]
0 ]
O M 3 /[P F D ]
O M 2
O M 1
O M 0
1
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 0
1 1
1 2
1 3
1 4
1 9
1 8
1 7
1 6
1 5
P A 4 /P W M 0 /T C 1
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
V D D
P C 5 /X T 1
P C 4 /X T 2
P C 3 /P W M 1
P C 2
P D 3
P D 2
P B 5 /[IN T ]
P B 4 /[T C 0 ]
P B 3 /S C O M 3 /[P F D ]
P C 7 /A N
P C 0 /A N
P C 1 /A N
P E
P E
P E
P E
P E
P E
P E
P E
4
5
0
4
3
V
P A 7 /R
P A 6 /O S
P A 5 /O S
P A 4 /P W M 0 /T
P A 3 /IN T /A
P A 2 /T C 0 /A
P A 1 /P F D /A
P A 0 /A
V
P C 6 /A
D D
E S
C 1
C 2
C 1
N 3
N 2
N 1
N 0
S S
N 6
7
1
2
4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4
3 3
3 2
3 1
5
3 0
6
1
2
3
7
H T 4 6 R 0 6 7
4 4 L Q F P -A
8
9
2 9
2 8
2 7
2 6
2 5
4
5
6
7
1 0
1 1
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
2 4
2 3
P C 5
P C 4
P C 3
P C 2
P D 7
P D 6
P D 5
P D 4
P D 3
P D 2
P F 1
/X T
/X T
/P W
/P W
2
1
M 1
M 2
/T C 2
P A 3 /IN T /A N 3
P A 2 /T C 0 /A N 2
1
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 0
1 1
1 2
1 5
1 4
1 3
P A 4 /P W M 0 /T C 1
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
V D D
P C 5 /X T 1
P C 4 /X T 2
P C 3 /P W M 1
P C 2 /P W M 2
P B 5 /[IN T ]
P B 4 /[T C 0 ]
P B 3 /S C O M 3 /[P F D ]
P A 1 /P F D /A N 1
P A 0 /A N 0
V S S
P C 6 /A N 6
P C 7 /A N 7
P C 0 /A N 4
P C 1 /A N 5
P D 0
P D 1
P B 0 /S C O M 0
P B 1 /S C O M 1
P B 2 //S C O M 2
9
8
7
6
5
4
3
2
P F 0
P B 7
P B 6
P B 5
P B 4
P B 3
P B 2
P B 1
P B 0
P D 1
P D 0
H T 4 6 R 0 6 7
2 8 S K D IP -A /S O P -A /S S O P -A
/[IN
/[T C
/S C
/S C
/S C
/S C
T ]
0 ]
O M 3 /[P F D ]
O M 2
O M 1
O M 0
1
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 0
1 1
1 2
1 3
1 4
1 9
1 8
1 7
1 6
1 5
P A 4 /P W M 0 /T C 1
P A 5 /O S C 2
P A 6 /O S C 1
P A 7 /R E S
V D D
P C 5 /X T 1
P C 4 /X T 2
P C 3 /P W M 1
P C 2 /P W M 2
P D 3
P D 2 /T C 2
P B 5 /[IN T ]
P B 4 /[T C 0 ]
P B 3 /S C O M 3 /[P F D ]
Rev. 1.30
4
January 22, 2013
HT46R064/065/066/0662/067
Pin Description
HT46R064
Pin Name
Function
PA0
PA0/AN0
AN0
PA1
PA1/PFD/AN1
PFD
AN1
PA2
PA2/TC0/AN2
TC0
AN2
PA3
PA3/INT/AN3
INT
AN3
PA4
PA4/PWM0
PWM0
PA5
PA5/OSC2
OSC2
PA6
PA6/OSC1
OSC1
PA7
PA7/RES
RES
PB0~PB5
PC0~PC3
VDD
VSS
Note:
PBn
PCn
VDD
VSS
CO
PBPU
PCPU
¾
¾
ST
ST
ST
PWR
PWR
OPT
PAPU
PAWK
ADCR
PAPU
PAWK
CTRL0
ADCR
PAPU
PAWK
¾
ADCR
PAPU
PAWK
¾
ADCR
PAPU
PAWK
CTRL0
PAPU
PAWK
CO
PAPU
PAWK
CO
PAWK
I/T
ST
AN
ST
¾
AN
ST
ST
AN
ST
ST
AN
ST
¾
ST
¾
ST
OSC
ST
O/T
Description
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
A/D channel 0
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CMOS PFD output
¾
A/D channel 1
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
¾
External Timer 0 clock input
A/D channel 2
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
¾
External interrupt input
A/D channel 3
CMOS General purpose I/O. Register enabled pull-up and wake-up.
CMOS PWM output
CMOS General purpose I/O. Register enabled pull-up and wake-up.
OSC
Oscillator pin
CMOS General purpose I/O. Register enabled pull-up and wake-up.
¾
Oscillator pin
NMOS General purpose I/O. Register enabled wake-up.
¾
Reset input
CMOS General purpose I/O. Register enabled pull-up.
CMOS General purpose I/O. Register enabled pull-up.
¾
¾
Power supply
Ground
I/T: Input type; O/T: Output type
OPT: Optional by configuration option (CO) or register option
PWR: Power; CO: Configuration option
ST: Schmitt Trigger input; CMOS: CMOS output; AN: analog input
SCOM= software controlled LCD COM
HXT: High frequency crystal oscillator
LXT: Low frequency crystal oscillator
Rev. 1.30
5
January 22, 2013
FPGA/CPLD
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