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AS7C33512FT32A-75TQI

Description
3.3V 512K x 32/36 Flow-through synchronous SRAM
Categorystorage    storage   
File Size508KB,19 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Download Datasheet Parametric View All

AS7C33512FT32A-75TQI Overview

3.3V 512K x 32/36 Flow-through synchronous SRAM

AS7C33512FT32A-75TQI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codeunknow
ECCN code3A991.B.2.A
Maximum access time7.5 ns
Other featuresFLOW-THROUGH ARCHITECTURE
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
memory density16777216 bi
Memory IC TypeSTANDARD SRAM
memory width32
Number of functions1
Number of terminals100
word count524288 words
character code512000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize512KX32
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
December 2004
®
AS7C33512FT32A
AS7C33512FT36A
3.3V 512K
×
32/36 Flow-through synchronous SRAM
Features
Organization: 524,288 words × 32 or 36 bits
Fast clock to data access: 7.5/8.5/10 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous flow-through operation
Asynchronous output enable control
Available in 100-pin TQFP packages
Individual byte write and global write
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[18:0]
19
Q0
Burst logic
Q1
19
D
Q
CE
Address
register
CLK
D
DQ
d
Q
Byte write
registers
CLK
D
DQ
Q
c
Byte write
registers
CLK
D
DQ
b
Q
Byte write
registers
CLK
D
DQ
a
Q
Byte write
registers
CLK
D
Enable
CE
register
CLK
Power
down
D
Enable
Q
delay
register
CLK
36/32
DQ[a:d]
Q
4
CLK
CE
CLR
17
19
512K × 32/36
Memory
array
GWE
BWE
BW
d
36/32
36/32
BW
c
BW
b
BW
a
CE0
CE1
CE2
OE
Output
buffer
Input
registers
CLK
ZZ
OE
Selection guide
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-75
8.5
7.5
275
90
60
-85
10
8.5
250
80
60
-10
12
10
230
80
60
Units
ns
ns
mA
mA
mA
12/23/04, v 1.4
Alliance Semiconductor
1 of 19
Copyright © Alliance Semiconductor. All rights reserved.
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