Features
•
High Performance RF-CMOS 2.4 GHz Radio Transceiver Targeted for IEEE 802.15.4
™
,
ZigBee
®
, 6LoWPAN, RF4CE, SP100, WirelessHART
™
and ISM Applications
•
Industry Leading Link Budget (104 dB)
– Receiver Sensitivity -101 dBm
– Programmable Output Power from -17 dBm up to +3 dBm
•
Ultra-Low Current Consumption:
–
SLEEP
=
0.02 µA
–
TRX_OFF
=
0.4 mA
–
RX_ON
=
12.3 mA
–
BUSY_TX
=
14 mA (at max. Transmit Power of +3 dBm)
•
Ultra-Low Supply Voltage (1.8V to 3.6V) with Internal Regulator
•
Optimized for Low BoM Cost and Ease of Production:
– Few External Components Necessary (Crystal, Capacitors and Antenna)
– Excellent ESD Robustness
Easy to Use Interface:
– Registers, Frame Buffer and AES Accessible through Fast SPI
– Only Two Microcontroller GPIO Lines Necessary
– One Interrupt Pin from Radio Transceiver
– Clock Output with Prescaler from Radio Transceiver
Radio Transceiver Features:
– 128-byte FIFO (SRAM) for Data Buffering
– Programmable Clock Output, to Clock the Host Microcontroller or as Timer
Reference
– Integrated RX/TX Switch
– Fully Integrated, Fast Settling PLL to support Frequency Hopping
– Battery Monitor
– Fast Wake-Up Time < 0.4 msec
Special IEEE 802.15.4-2006 Hardware Support:
– FCS Computation and Clear Channel Assessment
– RSSI Measurement, Energy Detection and Link Quality Indication
MAC Hardware Accelerator:
– Automated Acknowledgement, CSMA-CA and Retransmission
– Automatic Address Filtering
– Automated FCS Check
Extended Feature Set Hardware Support:
– AES 128-bit Hardware Accelerator
– RX/TX Indication (external RF Front-End Control)
– RX Antenna Diversity
– Supported PSDU data rates: 250 kb/s, 500 kb/s, 1 Mb/s and 2 Mb/s
– True Random Number Generation for Security Application
Industrial and Extended Temperature Range:
– -40°C to +85°C and -40°C to +125°C
I/O and Packages:
– 32-pin Low-Profile QFN Package 5 x 5 x 0.9 mm³
– RoHS/Fully Green
Compliant to IEEE 802.15.4-2006 and IEEE 802.15.4-2003
Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-T66, RSS-210
•
•
•
Low Power
2.4 GHz
Transceiver for
ZigBee,
IEEE 802.15.4,
6LoWPAN,
RF4CE, SP100,
WirelessHART,
and ISM
Applications
•
•
AT86RF231-ZU
AT86RF231-ZF
•
•
•
•
8111C–MCU Wireless–09/09
AT86RF231
1. Pin-out Diagram
Figure 1-1.
AT86RF231 Pin-out Diagram
X TA L 1
X TA L 2
A V DD
E V DD
AVSS
AVSS
AVSS
AVSS
D IG 3
D IG 4
AVSS
R FP
R FN
AVSS
D VSS
/R S T
32 31 30 29 28 27 26 25
24
1
exposed paddle
2
3
4
5
6
7
8
IR Q
/SEL
M OSI
D VSS
M IS O
SC LK
D VSS
C LKM
AVSS
23
22
21
20
19
18
A T86 R F2 3 1
17
9 10 11 12 13 14 15 16
D VSS
S L P _ TR
Note:
The exposed paddle is electrically connected to the die inside the package. It shall be soldered to
the board to ensure electrical and thermal contact and good mechanical stability.
DE V D D
DV D D
DV D D
D VSS
DI G 1
DI G 2
2
8111C–MCU Wireless–09/09
AT86RF231
1.1
Pin Descriptions
Pin Description AT86RF231
Name
DIG3
DIG4
AVSS
RFP
RFN
AVSS
DVSS
/RST
DIG1
Type
Digital output (Ground)
Digital output (Ground)
Ground
RF I/O
RF I/O
Ground
Ground
Digital input
Digital output (Ground)
Description
1. RX/TX Indicator, see
Section 11.5
2.
If disabled, pull-down enabled (AVSS)
1. RX/TX indicator (DIG3 inverted), see
Section 11.5
2. If disabled, pull-down enabled (AVSS)
Ground for RF signals
Differential RF signal
Differential RF signal
Ground for RF signals
Digital ground
Chip reset; active low
1. Antenna Diversity RF switch control, see
Section 11.4
2. If disabled, pull-down enabled (DVSS)
1. Antenna Diversity RF switch control (DIG1 inverted), see
Section 11.4
2. Signal IRQ_2 (RX_START) for RX Frame Time Stamping, see
Section 11.6
3. If functions disabled, pull-down enabled (DVSS)
Controls sleep, transmit start, receive states; active high, see
Section 6.5
Digital ground
Regulated 1.8V voltage regulator; digital domain, see
Section 9.4
Regulated 1.8V voltage regulator; digital domain, see
Section 9.4
External supply voltage; digital domain
Digital ground
Master clock signal output; low if disabled, see
Section 9.6
Digital ground
SPI clock
SPI data output (Master Input Slave Output)
Digital ground
SPI data input (Master Output Slave Input)
SPI select, active low
1. Interrupt request signal; active high or active low; configurable
2. Frame Buffer Empty Indicator; active high, see
Section 11.7
Crystal pin, see
Section 9.6
Crystal pin or external clock supply, see
Section 9.6
Analog ground
External supply voltage, analog domain
Table 1-1.
Pins
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DIG2
SLP_TR
DVSS
DVDD
DVDD
DEVDD
DVSS
CLKM
DVSS
SCLK
MISO
DVSS
MOSI
/SEL
IRQ
XTAL2
XTAL1
AVSS
EVDD
Digital output (Ground)
Digital input
Ground
Supply
Supply
Supply
Ground
Digital output
Ground
Digital input
Digital output
Ground
Digital input
Digital input
Digital output
Analog input
Analog input
Ground
Supply
3
8111C–MCU Wireless–09/09
AT86RF231
Table 1-1.
Pins
29
30
31
32
Paddle
Pin Description AT86RF231 (Continued)
Name
AVDD
AVSS
AVSS
AVSS
AVSS
Type
Supply
Ground
Ground
Ground
Ground
Description
Regulated 1.8V voltage regulator; analog domain, see
Section 9.4
Analog ground
Analog ground
Analog ground
Analog ground; Exposed paddle of QFN package
4
8111C–MCU Wireless–09/09
AT86RF231
1.2
1.2.1
Analog and RF Pins
Supply and Ground Pins
EVDD, DEVDD
EVDD and DEVDD are analog and digital supply voltage pins of the AT86RF231 radio
transceiver.
AVDD, DVDD
AVDD and DVDD are outputs of the internal 1.8V voltage regulators. The voltage regulators are
controlled independently by the radio transceivers state machine and are activated dependent
on the current radio transceiver state. The voltage regulators can be configured for external
supply.
For details, refer to
Section 9.4 “Voltage Regulators (AVREG, DVREG)” on page 110.
AVSS, DVSS
AVSS and DVSS are analog and digital ground pins respectively. The analog and digital power
domains should be separated on the PCB.
1.2.2
RF Pins
RFN, RFP
A differential RF port (RFP/RFN) provides common-mode rejection to suppress the switching
noise of the internal digital signal processing blocks. At board-level, the differential RF layout
ensures high receiver sensitivity by rejecting any spurious emissions originated from other digital
ICs such as a microcontroller.
A simplified schematic of the RF front end is shown in
Figure 1-2 on page 5.
Figure 1-2.
Simplified RF Front-end Schematic
PCB
AT86RF231
LNA
RX
RFP
RFN
PA
TX
0.9V
M0
CM
Feedback
RXTX
The RF port is designed for a 100Ω differential load. A DC path between the RF pins is allowed.
A DC path to ground or supply voltage is not allowed. Therefore, when connecting an RF-load
providing a DC path to the power supply or ground, AC-coupling is required as indicated in
Table
1-2 on page 6.
5
8111C–MCU Wireless–09/09
Mobile and portable
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