www.fairchildsemi.com
TMC2330A
Coordinate Transformer
16 x 16 Bit, 40 MOPS
Features
• Rectangular-to-Polar or Polar-to-Rectangular conversion
at guaranteed 40 MOPS pipelined throughput rate
• Polar data: 16-bit magnitude, 32-bit input/16-bit output
phase
• 16-bit user selectable two’s complement or sign-and-
magnitude rectangular data formats
• Input register clock enables and asynchronous output
enables simplify interfacing
• User-configurable phase accumulator for waveform
synthesis and amplitude, frequency, or phase modulation
• Magnitude output data overflow flag (in Polar-to-
Rectangular mode)
• Low power consumption CMOS process
• Single +5V power supply
• Available in a 120-pin plastic pin grid array package
(PPGA), 120-pin ceramic pin grid array package (CPGA),
120-pin MQFP to PPGA (MPGA) package, and 120-pin
metric quad flatpack package (MQFP)
Description
The TMC2330A VLSI circuit converts bidirectionally
between Cartesian (real and imaginary) and Polar (magnitude
and phase) coordinates at up to 40 MOPS (Million Operations
Per Second).
In its Rectangular-to-Polar mode, the TMC2330A can extract
phase and magnitude information or backward “map” from a
rectangular raster display to a radial (e.g., range-and-azimuth)
data set.
The Polar-to-Rectangular mode executes direct digital waveform
synthesis and modulation. The TMC2330A greatly simplifies
real-time image-space conversion between the radially-generated
image scan data found in radar, sonar, and medical imaging
systems, and raster display formats.
All input and output data ports are registered, and a new trans-
formed data word pair is available at the output every clock
cycle. The user-configurable phase accumulator structure,
input clock enables, and asynchronous three-state output bus
enables simplify interfacing. All signals are TTL compatible.
Fabricated in a submicron CMOS process, the TMC2330A
operates at up to the 40 MHz maximum clock rate over the full
commercial (0 to 70°C) temperature and supply voltage ranges,
and is available in 120-pin plastic pin grid array, 120-pin
ceramic pin grid array, 120-pin metric quad flatpack to PPGA
package, and 120-pin metric quad flatpack packages.
Applications
•
•
•
•
•
Scan conversion (phased array to raster)
Vector magnitude estimation
Range and bearing derivation
Spectral analysis
Digital waveform synthesis, including quadrature
functions
• Digital modulation and demodulation
Logic Symbol
ENXR
16
XRIN
15-0
DATA
INPUTS
ENYP
1-0
32
YPIN
31-0
OEPY
2
ACC
1-0
CONFIGURATION
CONTROLS
TCXY
RTP
CLK
OVF
16
PYOUT
15-0
16
RXOUT
15-0
DATA
OUTPUTS
OERX
TMC2330A
REV. 1.1.8 10/31/00
PRODUCT SPECIFICATION
TMC2330A
Block Diagram
XRIN
15-0
ENXR
YPIN
31-0
ENYP
1-0
ACC
1
ACC
0
16
32
32
2
1
2
M
C
32
AM
32
32
32
PM
32
FM
16
16
32
2
3
3
16
16
TCXY
RPT
TRANSFORMATION PROCESS
4-21
16
4-21
16
22
16
22
22
16
OERX
OVF
RXOUT
15-0
PYOUT
15-0
OEPY
Functional Description
The TMC2330A converts between Rectangular (Cartesian)
and Polar (Phase and Magnitude) coordinate data word pairs.
The user selects the numeric format and transformation to be
performed (Rectangular-To-Polar or Polar-To-Rectangular),
and the operation is performed on the data presented to the
inputs on the next clock. The transformed result is then
available at the outputs 22 clock cycles later, with new out-
put data available every 20ns with a 40 MHz clock. All input
and output data ports are registered, with input clock enables
and asynchronous high-impedance output enables to sim-
plify connections to system buses.
When executing a Rectangular-To-Polar conversion, the input
ports accept 16-bit Rectangular coordinate words, and the out-
put ports generate 16-bit magnitude and 16-bit phase data. The
user selects either two’s complement or sign-and-magnitude
Cartesian data format. Polar magnitude data are always in
magnitude format only. Since the phase angle word is modulo
2
π
, it may be regarded as either unsigned or two’s complement
format (Tables 1 and 2)
.
In Polar-To-Rectangular mode, the input ports accept 16-bit
Polar magnitude and 32-bit phase data, and the output ports
produce 16-bit Rectangular data words. Again, the user
selects between two’s complement or sign-and-magnitude
Cartesian data format.
2
REV. 1.1.8 10/31/00
TMC2330A
PRODUCT SPECIFICATION
Table 1. Data Input/Output Formats—Integer Format
Port
XRIN
XRIN
XRIN
YPIN
YPIN
YPIN
RXOUT
RXOUT
RXOUT
PYOUT
PYOUT
PYOUT
RTP
0
1
1
0
1
1
0
0
1
0
0
1
TCXY
X
0
1
X
0
1
0
1
X
0
1
X
±2
0
Bit #
31
30
29
…
16
15
2
15
14
2
14
2
14
2
14
2
-17
…
…
…
…
…
0
2
0
2
0
2
0
2
-31
Format
U
S
T
(x
π
)T/U
S
T
NS
–2
15
2
-1
2
14
2
14
2
-2
2
13
2
13
NS
–2
15
…
…
2
-15
2
0
2
0
2
-16
NS
–2
15
2
15
2
14
2
14
2
14
2
14
2
14
2
-1
2
0
2
0
2
0
2
0
2
0
2
-15
S
T
U
S
T
(x
π
)T/U
NS
–2
15
±2
0
Table 2. Data Input/Output Formats—Fractional Format
Port
XRIN
XRIN
XRIN
YPIN
YPIN
YPIN
RXOUT
RXOUT
RXOUT
PYOUT
PYOUT
PYOUT
Bit #
RTP
0
1
1
0
1
1
0
0
1
0
0
1
TCXY
X
0
1
X
0
1
0
1
X
0
1
X
±2
0
31
30
29
…
16
15
2
0
14
2
-1
2
-1
2
-1
2
-17
…
…
…
…
…
0
2
-15
2
-15
2
-15
2
-31
Format
U
S
T
(x
π
)T/U
S
T
NS
–2
0
2
-1
2
-1
2
-1
2
-2
2
-2
2
-2
NS
-2
0
…
…
…
2
-15
2
-15
2
-15
2
-16
NS
–2
0
2
0
2
-1
2
-1
2
-1
2
-1
2
-1
2
-1
…
…
…
…
…
…
2
-15
2
-15
2
-15
2
-15
2
-15
2
-15
S
T
U
S
T
(x
π
)T/U
NS
–2
0
±2
0
Notes:
1. -2
15
denotes two’s complement sign bit.
2. NS denotes negative sign, i.e., ‘1’ negates the number.
3. ±2
0
denotes two’s complement sign or highest magnitude bit – since phase angles are modulo 2
π
and phase accumulator is
modulo 2
32
, this bit may be regarded as +
π
or -
π
.
4. All phase angles are in terms of
π
radians, hence notation “x
π
.”
5. If A
CC
= 00, YPIN(15-0) are “don’t cares.”
6. Formats:
T = Two’s Complement
S = Signed Magnitude
U = Unsigned
HEX
FFFF
…
8001
8000
7FFF
…
0001
0000
U
65535
…
32769
32768
32767
…
1
0
T
–1
…
-32767
-32768
32767
…
1
0
S
-32767
…
-1
0
32767
…
1
0
REV. 1.1.8 10/31/00
3
PRODUCT SPECIFICATION
TMC2330A
Static Control Inputs
The controls RTP and TCXY determine the transformation
mode and the assumed numeric format of the Rectangular
data. The user must exercise caution when changing either of
these controls, as the new transformed results will not be
seen at the outputs until the entire internal pipe (22 clocks)
has been flushed. Thus, these controls are considered static.
Pin Assignments
120-Pin MQFP
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Name
VDD
PYOUT4
PYOUT3
GND
PYOUT2
PYOUT1
PYOUT0
VDD
OEPY
GND
RTP
CLK
GND
TCXY
ENPY
GND
ENPY1
ACC0
ACC1
VDD
YPIN0
YPIN1
YPIN2
YPIN3
YPIN4
YPIN5
YPIN6
GND
YPIN7
YPIN8
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Name
GND
YPIN9
YPIN10
VDD
YPIN11
YPIN12
YPIN13
YPIN14
YPIN15
YPIN16
YPIN17
VDD
YPIN18
YPIN19
YPIN20
GND
YPIN21
YPIN22
YPIN23
VDD
YPIN24
YPIN25
YPIN26
YPIN27
YPIN28
YPIN29
YPIN30
YPIN31
ENXR
XRIN0
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Name
VDD
XRIN1
XRIN2
GND
XRIN3
XRIN4
XRIN5
GND
XRIN6
XRIN7
XRIN8
XRIN9
XRIN10
XRIN11
XRIN12
GND
XRIN13
XRIN14
XRIN15
VDD
OERX
GND
RXOUT15
VDD
RXOUT14
RXOUT13
RXOUT12
GND
RXOUT11
RXOUT10
Pin
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Name
VDD
RXOUT9
RXOUT8
GND
RXOUT7
RXOUT6
RXOUT5
GND
RXOUT4
RXOUT3
RXOUT2
VDD
RXOUT1
RXOUT0
OVF
GND
PYOUT15
PYOUT14
PYOUT13
VDD
PYOUT12
PYOUT11
PYOUT10
GND
PYOUT9
PYOUT8
PYOUT7
GND
PYOUT6
PYOUT5
Pin 1
4
REV. 1.1.8 10/31/00
TMC2330A
PRODUCT SPECIFICATION
Pin Assignments
(continued)
120-Pin PPGA, H5 Package and 120-Pin CPGA, G1 Package and 120-Pin Metric Quad Flatpack to
120-Pin Plastic Pin Array, H6 Package
1
A
B
C
D
E
F
G
H
J
K
L
M
N
Top View
Cavity Up
KEY
2
3
4
5
6
7
8
9
10 11 12 13
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
C1
C2
C3
C4
Name
PYOUT5
PYOUT7
PYOUT8
PYOUT10
PYOUT12
PYOUT14
PYOUT15
RXOUT0
RXOUT2
RXOUT4
RXOUT6
RXOUT8
RXOUT10
PYOUT3
PYOUT4
PYOUT6
PYOUT9
PYOUT11
PYOUT13
OVF
RXOUT1
RXOUT3
RXOUT5
RXOUT7
RXOUT9
RXOUT12
PYOUT1
PYOUT2
VDD
GND
Pin
C5
C6
C7
C8
C9
C10
C11
C12
C13
D1
D2
D3
D11
D12
D13
E1
E2
E3
E11
E12
E13
F1
F2
F3
F11
F12
F13
G1
G2
G3
Name
GND
VDD
GND
VDD
GND
GND
VDD
RXOUT11
RXOUT13
OEPY
PYOUT0
GND
GND
RXOUT14
RXOUT15
RTP
GND
VDD
VDD
GND
OERX
TCKY
GND
CLK
VDD
RXIN15
RXIN14
ENPY1
ENPY0
GND
Pin
G11
G12
G13
H1
H2
H3
H11
H12
H13
J1
J2
J3
J11
J12
J13
K1
K2
K3
K11
K12
K13
L1
L2
L3
L4
L5
L6
L7
L8
L9
Name
GND
XRIN12
RXIN13
ACCO
ACC1
VDD
XRIN9
XRIN10
XRIN11
YPIN0
YPIN1
YPIN3
GND
XRIN7
XRIN8
YPIN2
YPIN4
GND
GND
XRIN5
XRIN6
YPIN5
YPIN7
GND
VDD
YPIN14
VDD
GND
VDD
YPIN27
Pin
L10
L11
L12
L13
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
Name
YPIN31
VDD
XRIN3
XRIN4
YPIN6
YPIN9
YPIN11
YPIN13
YPIN16
YPIN18
YPIN20
YPIN23
YPIN25
YPIN28
ENXR
XRIN1
XRIN2
YPIN8
YPIN10
YPIN12
YPIN15
YPIN17
YPIN19
YPIN21
YPIN22
YPIN24
YPIN26
YPIN29
YPIN30
XRIN0
Pin Descriptions
Pin Number
Pin Name
MQFP
CPGA/PPGA/
MPGA
Description
Power, Ground and Clock
V
DD
1, 8, 20, 34, 42, C3, E3, H3, L4, L6, The TMC2330A operates from a single +5V supply. All
50, 61, 80, 84, 91, L8, L11, F11, E11, power and ground pins must be connected.
102, 110
C11, C8, C6
4, 10, 13, 16, 28, D3, E2, F2, G3,
31, 46, 64, 68, 76, K3, L3, L7, K11,
82, 88, 94, 98,
J11, G11, E12,
106, 114, 118
D11, C10, C9, C7,
C5, C4
Ground
GND
REV. 1.1.8 10/31/00
5
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