High-Performance Fractional-N
Frequency Synthesizer
ICS8430002
DATA SHEET
General Description
The ICS8430002 is a general purpose, high-
performance, fractional-n LVPECL frequency
HiPerClockS™
synthesizer which can generate frequencies for a wide
variety of applications with output frequency step sizes
of <10ppm. The ICS8430002 has a 2:1 input
Multiplexer from which either a crystal input or a differential input can
be selected. The differential input can be wired to accept
single-ended signals (see the applications section of this datasheet).
Features
•
•
•
•
•
•
•
•
•
6-Bit Integer and 12-Bit Fractional Feedback Divider
Dual differential 3.3V LVPECL outputs which can be set
independently for either 3.3V or 2.5V
2:1 Input Mux:
One differential input
One crystal oscillator interface
PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
Output frequency range: 30.625MHz to 640MHz
Crystal input frequency range: 12MHz to 40MHz
VCO range: 490MHz to 650MHz
Parallel or serial interface for programming feedback divider and
output dividers
Supply voltage modes:
Core/Outputs:
3.3V/3.3V
3.3V/2.5V
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
ICS
Each of the differential LVPECL outputs has an output divider which
can be independently set so that two different frequencies can be
generated. Additionally, each LVPECL output pair has a dedicated
power supply pin so the outputs can run at 3.3V or 2.5V. The
ICS8430002 also supplies a buffered copy of the reference clock or
crystal frequency on the single-ended REF_OUT pin which can be
enabled or disabled (disabled by default). The output frequency can
be programmed using either a serial or parallel programming
interface.
The device features a fractional feedback divider with a 6-bit integer
and 12-bit fractional value. The minimum step value of the feedback
divider is 1/4096.
•
•
Pin Assignment
P1
P0
M5
M4
M3
M2
M1
M0
VCO_SEL
nP_LOAD
nPCLK
PCLK
P2
NB0
NB1
NB2
OE_REF
OEA
OEB
V
CC
NA0
NA1
NA2
V
EE
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
ICS8430002
33
48 Lead LQFP
5
7mm x 7mm x 1.4mm
32
6
31
package body
7
30
8
29
Y Package
9
28
Top View
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
FOUTA
nFOUTA
V
CCO_A
FOUTB
nFOUTB
V
CCO_B
REF_OUT
V
CCO_REF
nc
TEST
V
CC
V
EE
nc
nc
XTAL_OUT
XTAL_IN
nc
nc
SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
ICS8430002AY REVISION C NOVEMBER 12, 2009
1
©2009 Integrated Device Technology, Inc.
ICS8430002 Data Sheet
HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
Block Diagram
OEA
Pullup
VCO_SEL
Pullup
XTAL_IN
OSC
XTAL_OUT
PCLK
nPCLK
Pullup/Pulldown
SEL
Pulldown
P[2:0]
Pulldown
OEB
Pullup
MR
Pulldown
OE_REF
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M5:M0
NA2:NA0
NB2:NB0
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
6
3
3
3
Pulldown
0
0
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
÷1
÷2
÷3
÷4
FOUTA
÷5
÷6
nFOUTA
÷8
÷16
V
CCO_A
÷1
÷2
V
CCO_B
FOUTB
÷3
÷4
nFOUTB
÷5
÷6
÷8
÷16
P_DIV
1
Phase
Detector
VCO
1
÷
M
V
CCO_REF
REF_OUT
Configuration Interface Logic
TEST
ICS8430002AY REVISION C NOVEMBER 12, 2009
2
©2009 Integrated Device Technology, Inc.
ICS8430002 Data Sheet
HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes the
operation using a 25MHz crystal or clock input. Valid PLL loop divider
values for different crystal or clock input frequencies are defined in
the Input Frequency Characteristics, Table 5, NOTE 1 and NOTE 2.
When a crystal is being used, there is no pre-divider therefore set P
= 1 when referencing all following equations on this page.
The ICS8430002 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. It
has a 2:1 multiplexer from which either a crystal input or a differential
input can be selected.
An external fundamental-mode quartz crystal can be used as the
input to the on-chip crystal oscillator. The range of allowable crystal
frequencies is 12MHz to 40MHz. When selected, the crystal
frequency is the reference frequency input to the phase detector. The
relationship between the VCO frequency, the crystal input frequency
and the M divider (M) is as follows:
F
VCO
=
XTAL
×
M
A differential input clock can also be used. (See the Application
Information section for
Wiring the Differential Input to Accept
Single-Ended Levels.)
The differential input is followed by a
pre-divider that divides down the clock input frequency. This allows
an equal or lower reference frequency for the phase detector. See
Table 3C for available pre-divider values. The pre-divider value is set
through the P[2:0] pins or by using the serial programming interface.
The output frequency of the pre-divider is the reference frequency
input to the phase detector. The input frequency range of the phase
detector is 9MHz to 50MHz. The relationship between the VCO
frequency, the clock input frequency, the pre-divider (P) and the M
divider (M) is as follows:
F
IN
F
VCO
=
--------
×
M
P
Using a 25MHz input, the M value integer-only range is shown in
Table 3B,
Programmable VCO Frequency Table, P = ÷1.
Valid M
values for which the PLL will achieve lock for a 25MHz reference are
defined as 19.6
≤
M
≤
25.6. For different reference frequencies, the
range of valid M values may be calculated as follows:
490MHz
---------------------
≤
M
≤
650MHz
-
---------------------
-
F
IN
⁄
P
F
IN
⁄
P
The output of the VCO is scaled by output dividers prior to being sent
to each of the LVPECL output buffers. The output divider settings and
output frequency ranges are shown in table 3D.
Combining all the values of input frequency, pre-divider setting,
integer and fractional feedback divider settings, and output divider
setting, the output frequency may be calculated. The frequency out is
defined as follows:
F
IN
M
F
VCO
-
-
F
OUT
=
-------------
=
--------
×
----
P
N
N
The fractional-n M divider is composed of a 6-bit integer portion and
a 12-bit fractional portion. The decimal value obtained from these
settings can be determined as follows:
M
FRAC
M
=
M
INT
+
------------------
4096
Where:M
INT
is the 6-bit integer portion
M
FRAC
is the 12-bit fractional portion
For a given required M divider, the value to program into the M
FRAC
register is calculated by taking the fractional portion and multiplying
by 4096. For example, assuming a 25MHz crystal is being used, and
the desired VCO frequency is 515.625 (to support ethernet with
64B/66B encoding) the feedback setting required would be 20.625.
The integer portion of this number (20) is programed into the M
INT
register. The fractional portion (0.625) is multiplied by 4096. The
result (2560) is programmed into the M
FRAC
register. The full M
divider setting is then:
20
+
2560
=
20.625
-----------
-
4096
The frequency step size in ppm can be calculated using the following:
F
0
–
F
1
6
stepsize
=
-----------------
×
10 ppm
F
0
F
IN
M
-
Substituting the combined equation
--------
×
----
for the F terms in the
P
N
step size equation, the equation can be reduced to just the change in
M values.
M
0
–
M
1
6
stepsize
=
---------------------
×
1
×10
ppm
M
0
Input Min (MHz)
9
18
36
45
72
144
225
288
Input Max (MHz)
50
100
200
250
400
800
800
800
Pre-Divider
÷1
÷2
÷4
÷5
÷8
÷16
÷25
÷32
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. The VCO of the PLL operates over a range of
490MHz to 650MHz. Note that for some values of M (either too high
or too low), the PLL will not achieve lock.
ICS8430002AY REVISION C NOVEMBER 12, 2009
3
©2009 Integrated Device Technology, Inc.
ICS8430002 Data Sheet
HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
Assuming a 25MHz reference frequency and a VCO frequency of
637.5MHz (which, with an output divider of 6 would give an output
frequency of 106.25MHz, a common Fibre channel reference
frequency), requires an M setting of 25.5 (the integer portion being
25 and the fractional portion being 2048/4096). If you decrease the
fractional portion of the M divider by one bit (from 2048 to 2047), the
frequency change in ppm is calculated by:
6
stepsize
=
(
25.5
–
25.499755859375
) ×
1
×10
ppm
----------------------------------------------------------------
25.5
initially LOW. The data on the M, NA, and NB inputs are passed
directly to the M divider and both N output dividers. On the
LOW-to-HIGH transition of the nP_LOAD input, the data is latched
and the M and N dividers remain loaded until the next LOW transition
on nP_LOAD or until a serial event occurs. As a result, the M and Nx
bits can be hardwired to set the M divider and Nx output divider to a
specific default state that will automatically occur during power-up.
The TEST output is LOW when operating in the parallel input mode.
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the P pre-divider, M divider and Nx output divider when
S_LOAD transitions from LOW-to-HIGH. The P pre-divider, M divider
and Nx output divider values are latched on the HIGH-to-LOW
transition of S_LOAD. The serial mode can be used to program the
P, M and Nx bits and test bits T1 and T0. The data bits are clocked in
the following order as in the table below.
Which, for these conditions, is a step size of 9.6 ppm.
The ICS8430002 supports either serial or parallel programming
modes to program the P pre-divider, M feedback divider and N output
divider, however the parallel interface can only program the integer
portion of the feedback divider. The fractional portion of the feedback
divider must be programmed serially.
Figure 1
shows the timing
diagram for each mode. In parallel mode, the nP_LOAD input is
T1
T0
NB2
NB1
NB0
NA2
NA1
NA0
P2
P1
P0
DS1
DS0
...
M
FRAC
11
M
FRAC
10
M
FRAC
9
M
FRAC
8
M
FRAC
7
M
FRAC
6
M
FRAC
5
M
FRAC
4
M
FRAC
3
M
FRAC
2
M
FRAC
1
M
FRAC
0
...
M
INT
5
M
INT
4
M
INT
3
M
INT
2
M
INT
1
M
INT
0
S
ERIAL
L
OADING
S_CLOCK
S_DATA
t
S_LOAD
nP_LOAD
S
t
H
P
ARALLEL
L
OADING
M, N, P
t
S
M[5:0], NX[2:0], P[2:0]
nP_LOAD
t
S
t
H
S_LOAD
Time
Figure 1. Parallel & Serial Load Operations
ICS8430002AY REVISION C NOVEMBER 12, 2009
4
©2009 Integrated Device Technology, Inc.
ICS8430002 Data Sheet
HIGH-PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER
The internal registers T0 and T1 determine the state of the TEST
output as follows:
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_DATA, Shift Register Output
Reserved
Reserved
The function of the DS1, and DS0 bits is as follows:
DS1
0
1
0
1
DS0
0
1
1
0
Function
Integer Mode Only
Fractional Mode Only
Do Not Use
Do Not Use
Table 1. Pin Descriptions
Number
1, 47, 48
2, 3
4
5
Name
P2, P0, P1
NB0, NB1
NB2
OE_REF
Input
Input
Input
Input
Type
Pulldown
Pullup
Pulldown
Pulldown
Description
Pre-divider control input pins. See table 3C. LVCMOS/LVTTL interface levels.
Determines output divider value as defined in Table 3D, Function Table.
LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of REF_OUT output. When HIGH,
the output is active. When LOW, the output is high-impedance. LVCMOS/LVTTL
interface levels.
Output enable. Controls enabling and disabling of FOUTA, nFOUTA outputs.
When HIGH, the outputs are active. When LOW, the true output is low and the
compliment output is high. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTB, nFOUTB outputs.
When HIGH, the outputs are active. When LOW, the true output is low and the
compliment output is high. LVCMOS/LVTTL interface levels.
Core supply pins.
Pullup
Pulldown
Determines output divider value as defined in Table 3D, Function Table.
LVCMOS/LVTTL interface levels.
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Differential output pair for the synthesizer. LVPECL interface levels.
Output supply pin for FOUTA/nFOUTA LVPECL outputs.
Differential output pair for the synthesizer. LVPECL interface levels.
Output supply pin for FOUTB/nFOUTB LVPECL outputs.
Reference clock output. LVCMOS/LVTTL interface levels.
Output supply pin for REF_OUT.
No internal connection.
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs FOUTx to go low and the inverted outputs nFOUTx to go
high. When Logic LOW, the internal dividers and the outputs are enabled.
Assertion of MR does not affect loaded M, N, and T values.
LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register on the rising
edge of S_CLOCK. LVCMOS/LVTTL interface levels.
6
OEA
Input
Pullup
7
8, 14
9, 10
11
12, 24
13
15, 16
17
18, 19
20
21
22
23, 31, 32,
35, 36
OEB
V
CC
NA0, NA1
NA2
V
EE
TEST
FOUTA,
nFOUTA
V
CCO_A
FOUTB,
nFOUTB
V
CCO_B
REF_OUT
V
CCO_REF
nc
Input
Power
Input
Input
Power
Output
Output
Power
Output
Power
Output
Power
Unused
Pullup
25
MR
Input
Pulldown
26
S_CLOCK
Input
Pulldown
continued on next page.
ICS8430002AY REVISION C NOVEMBER 12, 2009
5
©2009 Integrated Device Technology, Inc.
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