EtronTech
Etron Confidential
EM68916DVAA
Advanced (Rev. 1.0 Apr. /2009)
Table 1. Ordering Information
Part Number
EM68916DVAA-6H
EM68916DVAA-75H
Clock
Frequency
166MHz
133MHz
Data Rate
IDD6 Package
8M x 16 Mobile DDR Synchronous DRAM (SDRAM)
Features
Fast clock rate: 166/133 MHz
Differential Clock CK &
CK
Bi-directional DQS
Four internal banks, 2M x 16-bit for each bank
Edge-aligned with read data, centered in write
data
•
Programmable Mode and Extended Mode Registers
-
CAS
Latency: 2, or 3
- Burst length: 2, 4, or 8
- Burst Type: Sequential & Interleaved
- PASR (Partial Array Self Refresh)
- Auto TCSR (Temperature Compensated Self
Refresh)
- DS (Drive Strength)
•
Individual byte writes mask control
•
DM Write Latency = 0
•
Precharge Standby Current = 100
µA
•
Self Refresh Current = 200
µA
•
Deep power-down Current = 10
µA
max. at 85
℃
•
Auto Refresh and Self Refresh
•
4096 refresh cycles / 64ms
•
No DLL (Delay Lock Loop), to reduce power; CK to
DQS is not synchronized.
•
Power supplies: V
DD
& V
DDQ
= +1.8V+0.15V/-0.1V
•
Interface: LVCMOS
•
Ambient Temperature T
A
= -25 ~ 85
℃
,
•
60-ball 8mm x 10mm VFBGA package
- Pb free and Halogen free
•
•
•
•
•
333Mbps/pin 200
µA
VFBGA
266Mbps/pin 200
µA
VFBGA
VA: indicates VFBGA package
A: indicates Generation Code
H: indicates Pb and Halogen Free for VFBGA Package
Figure 1. Ball Assignment (Top View)
1
A
B
C
D
E
F
G
H
J
K
VSS
2
DQ15
3
VSSQ
…
7
VDDQ
8
DQ0
9
VDD
VDDQ
DQ13
DQ14
DQ1
DQ2
VSSQ
VSSQ
DQ11
DQ12
DQ3
DQ4
VDDQ
VDDQ
DQ9
DQ10
DQ5
DQ6
VSSQ
VSSQ
UDQS
DQ8
DQ7
LDQS
VDDQ
VSS
UDM
NC
NC
LDM
VDD
CKE
CK
CK
WE
CAS
RAS
A9
A11
NC
CS
BA0
BA1
A6
A7
A8
A10/AP
A0
A1
VSS
A4
A5
A2
A3
VDD
Overview
The EM68916D is 134,217,728 bits of double data
rate synchronous DRAM organized as 4 banks of
2,097,152 words by 16 bits. The synchronous
operation with Data Strobe allows extremely high
performance. EM68916D is applied to reduce
leakage and refresh currents while achieving very
high speed. I/O transactions are possible on both
edges of the clock. The ranges of operating
frequencies, programmable burst length and
programmable latencies allow the device to be
useful for a variety of high performance memory
system applications.
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C.
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc. reserves the right to change products or specification without notice.
EtronTech
Figure 2. Block Diagram
CK
CK
CKE
SELF REFRESH
LOGIC & TIMER
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
EM68916DVAA
PASR, DS
CLOCK
BUFFER
EXTENDED
MODE
REGISTER
CS
RAS
CAS
WE
Row
Decoder
Row
Decoder
Row
Decoder
Row
Decoder
2M x 16
CELL ARRAY
(BANK #0)
Column Decoder
A10/AP
COLUMN
COUNTER
MODE
REGISTER
2M x 16
CELL ARRAY
(BANK #1)
Column Decoder
A0
A9
A11
BA0
BA1
LDQS
UDQS
DQ0
DQ15
~
~
ADDRESS
BUFFER
2M x 16
CELL ARRAY
(BANK #2)
Column Decoder
REFRESH
COUNTER
DATA
STROBE
BUFFER
DQ
Buffer
2M x 16
CELL ARRAY
(BANK #3)
Column Decoder
LDM
UDM
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EtronTech
Pin Descriptions
Table 2. Pin Details of EM68916D
Symbol
CK,
CK
Type
Input
Description
EM68916DVAA
Differential Clock:
CK and
CK
are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive edge of CK and
negative edge of
CK
. Input and output data is referenced to the crossing of CK
and
CK
(both directions of the crossing)
Clock Enable:
CKE activates (HIGH) and deactivates (LOW) the CK signal.
Internal clock signals and device input buffers and output drivers. Taking CKE Low
provides Precharge Power Down and Self Refresh operation (all banks idle) or
Active Power Down (Row Active in any bank). CKE is synchronous for all functions
except for disabling outputs, which is asynchronous. Input buffers, excluding
CK,
CK
and CKE, are disabled during Power Down and Self Refresh modes to
reduce standby power consumption.
Bank Activate:
BA0 and BA1 define to which bank the BankActivate, Read, Write,
or BankPrecharge command is being applied. BA0 and BA1 also determine which
mode register (MRS or EMRS) is loaded during a Mode Register Set command.
Address Inputs:
A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A8 with A10
defining Auto Precharge).
Chip Select:
CS
enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when
CS
is sampled HIGH.
CS
provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
Row Address Strobe:
The
RAS
signal defines the operation commands in
conjunction with the
CAS
and
WE
signals and is latched at the positive edges of
CK. When
RAS
and
CS
are asserted "LOW" and
CAS
is asserted "HIGH," either
the BankActivate command or the Precharge command is selected by the
WE
signal. When the
WE
is asserted "HIGH," the BankActivate command is selected
and the bank designated by BA is turned on to the active state. When the
WE
is
asserted "LOW," the Precharge command is selected and the bank designated by
BA is switched to the idle state after the precharge operation.
Column Address Strobe:
The
CAS
signal defines the operation commands in
conjunction with the
RAS
and
WE
signals and is latched at the positive edges of
CK. When
RAS
is held "HIGH" and
CS
is asserted "LOW," the column access is
started by asserting
CAS
"LOW." Then, the Read or Write command is selected
by asserting
WE
"HIGH " or LOW"."
CKE
Input
BA0, BA1
Input
A0-A11
Input
CS
Input
RAS
Input
CAS
Input
WE
Input
Write Enable:
The
WE
signal defines the operation commands in conjunction
with the
RAS
and
CAS
signals and is latched at the positive edges of CK. The
WE
input is used to select the BankActivate or Precharge command and Read or
Write command.
Bidirectional Data Strobe:
DQS is an output with read data and an input with
write data. DQS is edge-aligned with read data, centered in write data. It is used to
capture data. For x16, LDQS is DQS for DQ0-DQ7 and UDQS is DQS for DQ8-
DQ15.
LDQS, UDQS
Input /
Output
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EtronTech
LDM, UDM
Input
EM68916DVAA
Data Input Mask:
DM is an input mask signal for write data. Input data is masked
when DM is sampled High along with input data during a Write access. DM is
sampled on both edges of DQS. DM pins include dummy parasitic loading
internally to match the DQ and DQS loading. For x16, LDM is DM for DQ0-DQ7
and UDM is DM for DQ8-DQ15.
Data I/O:
The DQ0-DQ15 input and output data are synchronized with the positive
edges of CK and
CK
. The I/Os are byte-maskable during Writes.
Power Supply:
+1.8V+0.15V/-0.1V
Ground
DQ Power:
+1.8V+0.15V/-0.1V. Provide isolated power to DQs for improved noise
immunity.
DQ Ground:
Provide isolated ground to DQs for improved noise immunity.
No Connect:
No internal connection, these pins suggest to be left unconnected.
DQ0 – DQ15
V
DD
V
SS
V
DDQ
V
SSQ
NC
Input /
Output
Supply
Supply
Supply
Supply
-
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EtronTech
Operation Mode
EM68916DVAA
Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 3 shows
the truth table for the operation commands.
Table 3. Truth Table (Note (1), (2))
Command
BankActivate
BankPrecharge
PrechargeAll
Write
Write and AutoPrecharge
Read
Read and Autoprecharge
Mode Register Set
Extended Mode Register Set
No-Operation
Device Deselect
Burst Stop
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
Power Down Mode Entry
Power Down Mode Exit
Deep Power Down Entry
State
Idle
(3)
Any
Any
Active
(3)
Active
(3)
Active
(3)
Active
(3)
Idle
Idle
Any
Any
Active
(4)
Idle
Idle
Idle
(Self Refresh)
Idle/Active
(5
)
CKEn-1 CKEn DM BA1 BA0 A10
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
H
L
X
X
X
V
V
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
L
H
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
L
L
X
X
X
X
X
X
X
X
X
A11, A9-0
CS
RAS
CAS
Row Address
L
X
H
X
L
Column
H
Address
L
A0~A8
H
OP code
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Any
(Power Down)
Any
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
H
L
H
L
L
L
L
L
H
H
H
H
L
L
H
X
H
L
L
X
H
X
H
X
H
H
H
H
H
L
L
L
L
L
L
H
X
H
L
L
X
H
X
H
X
H
H
X
X
X
WE
H
L
L
L
L
H
H
L
L
H
X
L
H
H
X
H
X
H
X
H
L
X
X
X
Deep Power Down Exit
Any
L
H X X
X X
X
H
X
Data Write Enable
Active
H
X
L X
X X
X
X
X
Data Mask Disable
Active
H
X H X
X X
X
X
X
Note:
1. V = Valid data, X = Don't Care, L = Low level, H = High level
2. CKE
n
signal is input level when commands are provided.
CKE
n-1
signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA0, BA1signals.
4. Read burst stop with BST command for all burst types.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
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