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AS7C33512PFD18A-133TQIN

Description
3.3V 512K x 18 pipeline burst synchronous SRAM
Categorystorage    storage   
File Size496KB,20 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Environmental Compliance
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AS7C33512PFD18A-133TQIN Overview

3.3V 512K x 18 pipeline burst synchronous SRAM

AS7C33512PFD18A-133TQIN Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerALSC [Alliance Semiconductor Corporation]
Parts packaging codeQFP
package instructionLQFP, QFP100,.63X.87
Contacts100
Reach Compliance Codeunknow
ECCN code3A991.B.2.A
Maximum access time4.5 ns
Other featuresPIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)133 MHz
I/O typeCOMMON
JESD-30 codeR-PQFP-G100
JESD-609 codee3
length20 mm
memory density9437184 bi
Memory IC TypeSTANDARD SRAM
memory width18
Number of functions1
Number of terminals100
word count524288 words
character code512000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize512KX18
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Encapsulate equivalent codeQFP100,.63X.87
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)245
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum standby current0.03 A
Minimum standby current3.14 V
Maximum slew rate0.425 mA
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width14 mm
November 2004
®
AS7C33512PFD18A
3.3V 512K
×
18 pipeline burst synchronous SRAM
Features
Organization: 524,288 words × 18 bits
Fast clock speeds to 166 MHz
Fast clock to data access: 3.5/4.0 ns
Fast OE access time: 3.5/4.0 ns
Fully synchronous register-to-register operation
Dual-cycle deselect
Asynchronous output enable control
Individual byte write and global write
Available in 100-pin TQFP package
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Byte write enables
Multiple chip enables for easy expansion
3.3V core power supply
2.5V or 3.3V I/O operation with separate V
DDQ
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[18:0]
CLK
CS
CLR
Burst logic
Q
19
CS
Address
register
CLK
D
19
17 19
512K × 18
Memory
array
18
18
GWE
BW
b
BWE
BW
a
CE0
CE1
CE2
D
DQb
Q
CLK
D
DQa
Q
Byte Write
registers
Byte Write
registers
CLK
D
2
OE
CE
CLK
ZZ
Enable
register
Q
Output
registers
CLK
Input
registers
CLK
Power
down
D
Enable
Q
delay
register
CLK
OE
18
DQ[a,b]
Selection guide
–166
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
6
166
3.5
475
130
30
–133
7.5
133
4
425
100
30
Units
ns
MHz
ns
mA
mA
mA
12/1/04;
v.1.3
Alliance Semiconductor
1 of 20
Copyright © Alliance Semiconductor. All rights reserved.

AS7C33512PFD18A-133TQIN Related Products

AS7C33512PFD18A-133TQIN AS7C33512PFD18A AS7C33512PFD18A-133TQCN AS7C33512PFD18A-133TQI
Description 3.3V 512K x 18 pipeline burst synchronous SRAM 3.3V 512K x 18 pipeline burst synchronous SRAM 3.3V 512K x 18 pipeline burst synchronous SRAM 3.3V 512K x 18 pipeline burst synchronous SRAM
Is it Rohs certified? conform to - conform to incompatible
Maker ALSC [Alliance Semiconductor Corporation] - ALSC [Alliance Semiconductor Corporation] ALSC [Alliance Semiconductor Corporation]
Parts packaging code QFP - QFP QFP
package instruction LQFP, QFP100,.63X.87 - LQFP, QFP100,.63X.87 LQFP, QFP100,.63X.87
Contacts 100 - 100 100
Reach Compliance Code unknow - unknow unknow
ECCN code 3A991.B.2.A - 3A991.B.2.A 3A991.B.2.A
Maximum access time 4.5 ns - 4.5 ns 4.5 ns
Other features PIPELINED ARCHITECTURE - PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK) 133 MHz - 133 MHz 133 MHz
I/O type COMMON - COMMON COMMON
JESD-30 code R-PQFP-G100 - R-PQFP-G100 R-PQFP-G100
JESD-609 code e3 - e3 e0
length 20 mm - 20 mm 20 mm
memory density 9437184 bi - 9437184 bi 9437184 bi
Memory IC Type STANDARD SRAM - STANDARD SRAM STANDARD SRAM
memory width 18 - 18 18
Number of functions 1 - 1 1
Number of terminals 100 - 100 100
word count 524288 words - 524288 words 524288 words
character code 512000 - 512000 512000
Operating mode SYNCHRONOUS - SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 85 °C - 70 °C 85 °C
organize 512KX18 - 512KX18 512KX18
Output characteristics 3-STATE - 3-STATE 3-STATE
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LQFP - LQFP LQFP
Encapsulate equivalent code QFP100,.63X.87 - QFP100,.63X.87 QFP100,.63X.87
Package shape RECTANGULAR - RECTANGULAR RECTANGULAR
Package form FLATPACK, LOW PROFILE - FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE
Parallel/Serial PARALLEL - PARALLEL PARALLEL
Peak Reflow Temperature (Celsius) 245 - 245 NOT SPECIFIED
power supply 2.5/3.3,3.3 V - 2.5/3.3,3.3 V 2.5/3.3,3.3 V
Certification status Not Qualified - Not Qualified Not Qualified
Maximum seat height 1.6 mm - 1.6 mm 1.6 mm
Maximum standby current 0.03 A - 0.03 A 0.03 A
Minimum standby current 3.14 V - 3.14 V 3.14 V
Maximum slew rate 0.425 mA - 0.425 mA 0.425 mA
Maximum supply voltage (Vsup) 3.465 V - 3.465 V 3.465 V
Minimum supply voltage (Vsup) 3.135 V - 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V - 3.3 V 3.3 V
surface mount YES - YES YES
technology CMOS - CMOS CMOS
Temperature level INDUSTRIAL - COMMERCIAL INDUSTRIAL
Terminal surface MATTE TIN - MATTE TIN Tin/Lead (Sn/Pb)
Terminal form GULL WING - GULL WING GULL WING
Terminal pitch 0.65 mm - 0.65 mm 0.65 mm
Terminal location QUAD - QUAD QUAD
Maximum time at peak reflow temperature 30 - 30 NOT SPECIFIED
width 14 mm - 14 mm 14 mm
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