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AS7C3364NTD32B

Description
3.3V 64K x 32/36 Pipelined SRAM with NTD
File Size422KB,19 Pages
ManufacturerALSC [Alliance Semiconductor Corporation]
Download Datasheet View All

AS7C3364NTD32B Overview

3.3V 64K x 32/36 Pipelined SRAM with NTD

April 2005
®
AS7C3364NTD32B
AS7C3364NTD36B
3.3V 64K×32/36 Pipelined SRAM with NTD
TM
Features
• Organization: 65,536 words × 32 or 36 bits
• NTD
architecture for efficient bus operation
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.0/3.5/4.0 ns
• Fast OE access time: 3.0/3.5/4.0 ns
• Fully synchronous operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for reduced power standby
Logic block diagram
A[15:0]
16
D
Burst logic
CE0
CE1
CE2
Address
register
Q
16
16
D
16
Q
CLK
Write delay
addr. registers
CLK
16
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
Control
logic
Write Data Registers
CLK
CLK
128K x 32/36
SRAM
Array
DQ [a:d
]
32/36
D
Data
Q
Input
Register
CLK
32/36
32/36
32/36
32/36
CLK
CEN
CLK
OE
Output
Register
32/36
OE
DQ [a:d]
Selection Guide
-200
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
5
200
3.0
375
135
30
-166
6
166
3.5
350
120
30
-133
7.5
133
4
325
110
30
Units
ns
MHz
ns
mA
mA
mA
4/28/05; v.1.3
Alliance Semiconductor
P. 1 of 19
Copyright © Alliance Semiconductor. All rights reserved.
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