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MB91F526KSCPMC

Description
RISC Microcontroller, 32-Bit, FLASH, FR CPU, 80MHz, CMOS, PQFP144, LQFP-144
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size4MB,289 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

MB91F526KSCPMC Overview

RISC Microcontroller, 32-Bit, FLASH, FR CPU, 80MHz, CMOS, PQFP144, LQFP-144

MB91F526KSCPMC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCypress Semiconductor
package instructionLFQFP, QFP144,.87SQ,20
Reach Compliance Codecompliant
Has ADCYES
Address bus width22
bit size32
CPU seriesFR
maximum clock frequency16 MHz
DAC channelYES
DMA channelYES
External data bus width16
JESD-30 codeS-PQFP-G144
JESD-609 codee0
length16 mm
Number of I/O lines120
Number of terminals144
On-chip program ROM width8
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
PWM channelYES
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Encapsulate equivalent codeQFP144,.87SQ,20
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3/5 V
Certification statusNot Qualified
RAM (bytes)139264
rom(word)1114112
ROM programmabilityFLASH
Maximum seat height1.7 mm
speed80 MHz
Maximum slew rate115 mA
Maximum supply voltage5.5 V
Minimum supply voltage2.7 V
Nominal supply voltage3 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.4 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width16 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER, RISC
MB91520 Series
32-bit FR81S Microcontroller
The MB91520 series is a Cypress
32-bit
microcontroller designed for automotive devices. This series contains the FR81S CPU
which is compatible with the FR family.
Note:This
series is a composition of the end of the above-mentioned each name of articles of presence, According to Presence of
sub-clock, CSV initial value and LVD initial value. Please see
"ORDERING
INFORMATION" for details.
Features
FR81S CPU Core
32-bit
RISC, load/store architecture, pipeline 5-stage
structure
Maximum operating frequency:
80
MHz (Source oscillation
= 4.0 MHz and
20
multiplied
(PLL
clock multiplication
system))
General-purpose register : 32 bits
×
16 sets
16-bit
fixed length instructions
(basic
instruction),
1 instruction per cycle
Instructions appropriate to embedded applications
Memory-to-memory transfer instruction
Bit processing instruction
Barrel shift order etc.
High-level language support instructions
Function entry/exit instructions
Register
content multi-load and store instructions
Bit search instructions
Logical 1 detection, 0 detection, and change-point detection
Branch instructions with delay slot
Overhead reduction during branch process
Register interlock function
Easy assembler writing
The support at the built-in / instruction level of the multiplier
Signed 32-bit multiplication: 5 cycles
Signed 16-bit multiplication: 3 cycles
Interrupt
(PC/PS
saving)
6 cycles
(16
priority levels)
The Harvard architecture allows simultaneous execution of
program and data access.
Instruction compatibility with the FR Family
Built-in memory protection function
(MPU)
Eight protection areas can be specified commonly for
instructions and the data.
Control access privilege in both privilege mode and
user mode.
Built-in FPU (floating point arithmetic)
IEEE754 compliant
Floating-point register
32-bit
×
16 sets
Peripheral Functions
Clock generation (equipped with SSCG function)
Main oscillation (4MHz to 16MHz)
Sub oscillation
(32kHz)
or none sub oscillation
PLL multiplication rate : 1 to
20
times
Equipped with a 100kHz CR oscillator
Built-in program flash memory capacity
MB91F522:256+64KB
MB91F523:384+64KB
MB91F524:512+64KB
MB91F525:768+64KB
MB91F526:1024+64KB
Flash memory for built-in data (WorkFlash) 64KB
Built-in RAM capacity
Main RAM
MB91F522:48KB
MB91F523:48KB
MB91F524:64KB
MB91F525:96KB
MB91F526:128KB
Backup RAM 8KB
General-purpose ports:
MB91F52xB 44 sets (No sub oscillation), 42 sets (sub
oscillation)
MB91F52xD 56 sets (No sub oscillation), 54 sets (sub
oscillation)
MB91F52xF 76 sets (No sub oscillation), 74 sets (sub
oscillation)
MB91F52xJ
96 sets (No sub oscillation), 94 sets (sub
oscillation)
MB91F52xK 120 sets (No sub oscillation), 118 sets (sub
oscillation)
MB91F52xL 152 sets (No sub oscillation), 150 sets (sub
oscillation)
2
Included I C open drain corresponding ports:16 sets
External bus interface
22-bit
address, 16-bit data
DMA Controller
Up to 16 channels can be started simultaneously.
2 transfer factors
(Internal
peripheral request and
software)
A/D converter (successive approximation type)
12-bit
resolution : Max.48ch (32ch+16ch)
Conversion time :
1.4μs
198 Champion Court
San Jose, CA 95134-1709
408-943-2600
Cypress Semiconductor Corporation
Document Number:
002-04662
Rev. *D
Revised June 23, 2016
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