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935300449118

Description
Binary Counter, HCT Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, PDSO16
Categorylogic    logic   
File Size194KB,29 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
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935300449118 Overview

Binary Counter, HCT Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, PDSO16

935300449118 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNexperia
package instructionSSOP,
Reach Compliance Codecompliant
Counting directionBIDIRECTIONAL
seriesHCT
JESD-30 codeR-PDSO-G16
JESD-609 codee4
length6.2 mm
Load/preset inputYES
Logic integrated circuit typeBINARY COUNTER
Operating modeSYNCHRONOUS
Humidity sensitivity level1
Number of digits4
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
propagation delay (tpd)65 ns
Filter levelAEC-Q100
Maximum seat height2 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Trigger typePOSITIVE EDGE
width5.3 mm
minfmax13 MHz
74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
Rev. 1 — 12 July 2013
Product data sheet
1. General description
The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter.
Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs
change state synchronously with the LOW-to-HIGH transition of either clock input. If the
CPU clock is pulsed while CPD is held HIGH, the device counts up. If the CPD clock is
pulsed while CPU is held HIGH, the device counts down. Only one clock input can be held
HIGH at any time to guarantee predictable behavior. The device can be cleared at any
time by the asynchronous master reset input (MR). It may also be loaded in parallel by
activating the asynchronous parallel load input (PL). The terminal count up (TCU) and
terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the
maximum count state of 15, the next HIGH-to-LOW transition of CPU causes TCU to go
LOW. TCU remains LOW until CPU goes HIGH again, duplicating the count up clock.
Likewise, the TCD output goes LOW when the circuit is in the zero state and the CPD
goes LOW. The terminal count outputs duplicate the clock waveforms and can be used as
the clock input signals to the next higher-order circuit in a multistage counter. Multistage
counters are not fully synchronous, since there is a slight delay time difference added for
each stage that is added. The counter may be preset by the asynchronous parallel load
capability of the circuit. Information on the parallel data inputs (D0 to D3), is loaded into
the counter. This information appears on the outputs (Q0 to Q3) regardless of the
conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on
the master reset (MR) input disables the parallel load gates. It overrides both clock inputs
and sets all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a
reset or load operation, the next LOW-to-HIGH transition of that clock is interpreted as a
legitimate signal and it is counted. Inputs include clamp diodes that enable the use of
current limiting resistors to interface inputs to voltages in excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Input levels:
For 74HC193-Q100: CMOS level
For 74HCT193-Q100: TTL level
Synchronous reversible 4-bit binary counting
Asynchronous parallel load
Asynchronous reset
Expandable without external logic
Complies with JEDEC standard no. 7A

935300449118 Related Products

935300449118 74HC193DB-Q100 74HCT193DB-Q100 74HC193D-Q100 74HC193PW-Q100 74HCT193PW-Q100 935300444118
Description Binary Counter, HCT Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, PDSO16 Binary Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, PDSO16 Binary Counter, HCT Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, PDSO16 Binary Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, PDSO16 Binary Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, PDSO16 Binary Counter, HCT Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, PDSO16 Binary Counter, HC/UH Series, Synchronous, Positive Edge Triggered, 4-Bit, Bidirectional, CMOS, PDSO16
Is it Rohs certified? conform to conform to conform to conform to conform to conform to conform to
Maker Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia
package instruction SSOP, SSOP, SSOP, 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16 SSOP,
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant
Counting direction BIDIRECTIONAL BIDIRECTIONAL BIDIRECTIONAL BIDIRECTIONAL BIDIRECTIONAL BIDIRECTIONAL BIDIRECTIONAL
series HCT HC/UH HCT HC/UH HC/UH HCT HC/UH
JESD-30 code R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16
JESD-609 code e4 e4 e4 e4 e4 e4 e4
length 6.2 mm 6.2 mm 6.2 mm 9.9 mm 5 mm 5 mm 6.2 mm
Logic integrated circuit type BINARY COUNTER BINARY COUNTER BINARY COUNTER BINARY COUNTER BINARY COUNTER BINARY COUNTER BINARY COUNTER
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Humidity sensitivity level 1 1 1 1 1 1 1
Number of digits 4 4 4 4 4 4 4
Number of functions 1 1 1 1 1 1 1
Number of terminals 16 16 16 16 16 16 16
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SSOP SSOP SSOP SOP TSSOP TSSOP SSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
propagation delay (tpd) 65 ns 325 ns 65 ns 325 ns 325 ns 65 ns 325 ns
Filter level AEC-Q100 AEC-Q100 AEC-Q100 AEC-Q100 AEC-Q100 AEC-Q100 AEC-Q100
Maximum seat height 2 mm 2 mm 2 mm 1.75 mm 1.1 mm 1.1 mm 2 mm
Maximum supply voltage (Vsup) 5.5 V 6 V 5.5 V 6 V 6 V 5.5 V 6 V
Minimum supply voltage (Vsup) 4.5 V 2 V 4.5 V 2 V 2 V 4.5 V 2 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V
surface mount YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
Terminal surface Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au) Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm 0.65 mm 1.27 mm 0.65 mm 0.65 mm 0.65 mm
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL DUAL
Trigger type POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
width 5.3 mm 5.3 mm 5.3 mm 3.9 mm 4.4 mm 4.4 mm 5.3 mm
minfmax 13 MHz 15 MHz 13 MHz 15 MHz 15 MHz 13 MHz 15 MHz
Load/preset input YES YES YES - - - YES
Base Number Matches - 1 1 1 1 1 -

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