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A1460BP-1PQ208C

Description
Field Programmable Gate Array, 848 CLBs, 6000 Gates, 125MHz, 848-Cell, CMOS, PQFP208, PLASTIC, MO-143, QFP-208
CategoryProgrammable logic devices    Programmable logic   
File Size1MB,40 Pages
ManufacturerActel
Websitehttp://www.actel.com/
Download Datasheet Parametric View All

A1460BP-1PQ208C Overview

Field Programmable Gate Array, 848 CLBs, 6000 Gates, 125MHz, 848-Cell, CMOS, PQFP208, PLASTIC, MO-143, QFP-208

A1460BP-1PQ208C Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerActel
package instructionPLASTIC, MO-143, QFP-208
Reach Compliance Codeunknown
Other featuresMAX 167 I/OS
maximum clock frequency125 MHz
Combined latency of CLB-Max2.6 ns
JESD-30 codeS-PQFP-G208
JESD-609 codee0
length28 mm
Configurable number of logic blocks848
Equivalent number of gates6000
Number of entries168
Number of logical units848
Output times168
Number of terminals208
Maximum operating temperature70 °C
Minimum operating temperature
organize848 CLBS, 6000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeFQFP
Encapsulate equivalent codeQFP208,1.2SQ,20
Package shapeSQUARE
Package formFLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height4.1 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width28 mm
Accelerator Series FPGAs:
ACT 3 PCI-Compliant Family
F e a tu r es
• Up to 10,000 Gate Array Equivalent Gates.
• Up to 250 MHz On-Chip Performance.
• 9.0 ns Clock-to-Output.
• Up to 1,153 Dedicated Flip-Flops.
• Up to 228 User-Programmable I/O Pins.
• PCI-Compliant I/O Drivers.
• Four High-Speed, Low-Skew Clocks.
A CT 3 PC I -C ompl iant De vic es
Device
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages (40 Gates)
20-Pin PAL Equivalent Packages (100 Gates)
Logic Modules
S-Module
C-Module
Dedicated Flip-Flops
1
User I/Os (Maximum)
Packages
2
(By Pin Count)
PQFP
RQFP
TQFP
BGA
Performance
3
(Maximum, Worst-Case Commercial)
Chip-to-Chip
4
Accumulators (16-Bit)
Loadable Counter (16-Bit)
Prescaled Loadable Counters (16-Bit)
Datapath, Shift Registers
Clock-to-Output (Pad-to-Pad)
Notes:
1. One flip-flop per S-module, two flip-flops per I/O module.
2. See Product Plan on page 3 for package availability.
3. Based on A1460BP-2, and A14100BP-2.
4. Clock-to-Output + Set-Up
• Highly Predictable, Synthesis-Friendly Architecture
Supports High-Level Design Methodologies.
• 100% Module Utilization with Automatic Place and Route
Tools.
• Deterministic, User-Controllable Timing via DirectTime
Software Tool.
• VHDL and Verilog-HDL Models for PCI Target, Master, and
Bridge Functions.
A1460BP
6,000
15,000
150
60
848
432
416
768
168
160, 208
176
225
97 MHz
63 MHz
110 MHz
150 MHz
150 MHz
9.0 ns
A14100BP
10,000
25,000
250
100
1,377
697
680
1,153
228
208
313
93 MHz
63 MHz
105 MHz
150 MHz
150 MHz
9.5 ns
M ar ch 1 997
1
© 1997 Actel Corporation
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