MPC8379ECZQALGA datasheet, PDF

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MPC8379ECZQALGA: DescriptionMICROPROCESSOR; Categorysemiconductor The embedded processor and controller; File Size1MB，114 Pages; ManufacturerFREESCALE (NXP)

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MPC8379ECZQALGA Overview

MICROPROCESSOR

MPC8379ECZQALGA Parametric

Parameter Name	Attribute value
Number of terminals	689
Line speed	667 MHz
state	Active
microprocessor_microcontroller_peripheral_ic_type	MICROPROCESSOR
Number of digits	32
jesd_30_code	S-PBGA-B689
jesd_609_code	e2
moisture_sensitivity_level	3
Packaging Materials	PLASTIC/EPOXY
ckage_code	BGA
ckage_equivalence_code	BGA689,29X29,40
packaging shape	SQUARE
Package Size	GRID ARRAY
eak_reflow_temperature__cel_	260
wer_supplies	1,1.8/2.5,2.5/3.3
qualification_status	COMMERCIAL
sub_category	Microprocessors
surface mount	YES
Craftsmanship	CMOS
terminal coating	TIN COPPER/TIN SILVER
Terminal form	BALL
Terminal spacing	1 mm
Terminal location	BOTTOM
ime_peak_reflow_temperature_max__s_	40

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Freescale Semiconductor

Technical Data

Document Number: MPC8379EEC

Rev. 2, 10/2009

MPC8379E

™

PowerQUICC II Pro Processor

Hardware Specifications

This document provides an overview of the MPC8379E

PowerQUICC™ II Pro processor features, including a block

diagram showing the major functional components. The

device is a cost-effective, low-power, highly integrated host

processor that addresses the requirements of several printing

and imaging, consumer, and industrial applications,

including main CPUs and I/O processors in printing systems,

networking switches and line cards, wireless LANs

(WLANs), network access servers (NAS), VPN routers,

intelligent NIC, and industrial controllers. The MPC8379E

extends the PowerQUICC™ family, adding higher CPU

performance, additional functionality, and faster interfaces

while addressing the requirements related to time-to-market,

price, power consumption, and package size.

Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10

Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 14

DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . 16

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 22

USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Enhanced Secure Digital Host Controller (eSDHC) . 42

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 67

Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 77

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

System Design Information . . . . . . . . . . . . . . . . . . 108

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 110

Document Revision History . . . . . . . . . . . . . . . . . . 113

Overview

The MPC8379E incorporates the e300c4s core, which

includes 32 Kbytes of L1 instruction and data caches and

on-chip memory management units (MMUs). The device

offers two enhanced three-speed 10, 100, 1000 Mbps

Ethernet interfaces, a DDR1/DDR2 SDRAM memory

controller, a flexible, a 32-bit local bus controller, a 32-bit

PCI controller, an optional dedicated security engine, a USB

10.

11.

12.

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14.

15.

16.

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18.

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23.

24.

25.

26.

Overview

1.3

Dual Enhanced Three-Speed Ethernet Controllers (eTSECs)

The eTSECs include the following features:

• Two enhanced Ethernet interfaces can be used for RGMII/MII/RMII/RTBI

• Two controllers conform to IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z,

IEEE 802.3au, IEEE 802.3ab, and IEEE Std 1588™ standards

• Support for Wake-on-Magic Packet™, a method to bring the device from standby to full operating

mode

• MII management interface for external PHY control and status

1.4

Integrated Programmable Interrupt Controller (IPIC)

The integrated programmable interrupt controller (IPIC) implements the necessary functions to provide a

flexible solution for general-purpose interrupt control. The IPIC programming model is compatible with

the MPC8260 interrupt controller, and it supports 8 external and 34 internal discrete interrupt sources.

Interrupts can also be redirected to an external interrupt controller.

1.5

Power Management Controller (PMC)

The power management controller includes the following features:

• Provides power management when the device is used in both host and agent modes

• Supports PCI Power Management 1.2 D0, D1, D2, and D3hot states

• Support for PME generation in PCI agent mode, PME detection in PCI host mode

• Supports Wake-on-LAN (Magic Packet), USB, GPIO, and PCI (PME input as host)

• Supports MPC8349E backward-compatibility mode

1.6

Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) allows the device to exchange data between other PowerQUICC

family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time

clocks, A/D converters, and ISDN devices.

The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface

(receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an

independent baud-rate generator, and a control unit.

1.7

DMA Controller, Dual I

C, DUART, Enhanced Local Bus Controller

(eLBC), and Timers

The device provides an integrated four-channel DMA controller with the following features:

• Allows chaining (both extended and direct) through local memory-mapped chain descriptors

(accessible by local masters)

• Supports misaligned transfers

MPC8379E PowerQUICC

™

II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Overview

There are two I

C controllers. These synchronous, multi-master buses can be connected to additional

devices for expansion and system development.

The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550

programming models. 16-byte FIFOs are supported for both the transmitter and the receiver.

The main component of the enhanced local bus controller (eLBC) is its memory controller, which provides

a seamless interface to many types of memory devices and peripherals. The memory controller is

responsible for controlling eight memory banks shared by a NAND Flash control machine (FCM), a

general-purpose chip-select machine (GPCM), and up to three user-programmable machines (UPMs). As

such, it supports a minimal glue logic interface to SRAM, EPROM, NOR Flash EPROM, NAND Flash,

EPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other

peripherals. The eLBC external address latch enable (LALE) signal allows multiplexing of addresses with

data signals to reduce the device pin count.

The enhanced local bus controller also includes a number of data checking and protection features, such

as data parity generation and checking, write protection, and a bus monitor to ensure that each bus cycle

is terminated within a user-specified period. The local bus can operate at up to 133 MHz.

The system timers include the following features: periodic interrupt timer, real time clock, software

watchdog timer, and two general-purpose timer blocks.

1.8

Security Engine

The optional security engine is optimized to handle all the algorithms associated with IPSec,

IEEE 802.11i, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto

execution units (EUs). The execution units are:

• Data encryption standard execution unit (DEU), supporting DES and 3DES

• Advanced encryption standard unit (AESU), supporting AES

• Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-256, and HMAC with any

algorithm

• One crypto-channel supporting multi-command descriptor chains

1.9

PCI Controller

The PCI controller includes the following features:

•

PCI Specification Revision 2.3

compatible

• Single 32-bit data PCI interface operates at up to 66 MHz

• PCI 3.3-V compatible (not 5-V compatible)

• Support for host and agent modes

• On-chip arbitration, supporting 5 external masters on PCI

• Selectable hardware-enforced coherency

MPC8379E PowerQUICC

™

II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

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