MPC8533ECHXAAFB datasheet, PDF

Datasheet> All Categories > MPC8533ECHXAAFB

Preview

MPC8533ECHXAAFB: DescriptionPowerQUICCâ¢ III Integrated Processor Hardware Specifications; File Size1MB，116 Pages; ManufacturerFREESCALE (NXP)

Download Datasheet View All

MPC8533ECHXAAFB Overview

PowerQUICCâ¢ III Integrated Processor Hardware Specifications

Preview

Download Datasheet

View All

Freescale Semiconductor

Technical Data

Document Number: MPC8533EEC

Rev. 3, 11/2009

MPC8533E PowerQUICC™ III

Integrated Processor

Hardware Specifications

MPC8533E Overview

Contents

MPC8533E Overview . . . . . . . . . . . . . . . . . . . . . . . . . 1

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13

Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 16

DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 17

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Enhanced Three-Speed Ethernet (eTSEC),

MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Ethernet Management Interface Electrical

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Programmable Interrupt Controller . . . . . . . . . . . . . 51

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 60

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 78

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

System Design Information . . . . . . . . . . . . . . . . . . 102

Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 111

Document Revision History . . . . . . . . . . . . . . . . . . 114

This section provides a high-level overview of MPC8533E

features.

Figure 1

shows the major functional units within

the device.

1.1

Key Features

10.

11.

12.

13.

14.

15.

16.

17.

18.

19.

20.

21.

22.

23.

The following list provides an overview of the device feature

set:

• High-performance 32-bit Book E–enhanced core

built on Power Architecture™ technology:

— 32-Kbyte L1 instruction cache and 32-Kbyte L1

data cache with parity protection. Caches can be

locked entirely or on a per-line basis, with

separate locking for instructions and data.

— Signal-processing engine (SPE) APU (auxiliary

processing unit). Provides an extensive

instruction set for vector (64-bit) integer and

fractional operations. These instructions use both

the upper and lower words of the 64-bit GPRs as

they are defined by the SPE APU.

MPC8533E Overview

— Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)

floating-point instructions that use the 64-bit GPRs.

— 36-bit real addressing

— Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set

for single-precision (32-bit) floating-point instructions.

— Memory management unit (MMU). Especially designed for embedded applications. Supports

4-Kbyte–4-Gbyte page sizes.

— Enhanced hardware and software debug support

— Performance monitor facility that is similar to, but separate from, the device performance

monitor

The e500 defines features that are not implemented on this device. It also generally defines some features

that this device implements more specifically. An understanding of these differences can be critical to

ensure proper operations.

• 256-Kbyte L2 cache/SRAM

— Flexible configuration

— Full ECC support on 64-bit boundary in both cache and SRAM modes

— Cache mode supports instruction caching, data caching, or both.

— External masters can force data to be allocated into the cache through programmed memory

ranges or special transaction types (stashing).

– 1, 2, or 4 ways can be configured for stashing only.

— Eight-way set-associative cache organization (32-byte cache lines)

— Supports locking entire cache or selected lines. Individual line locks are set and cleared through

Book E instructions or by externally mastered transactions.

— Global locking and flash clearing done through writes to L2 configuration registers

— Instruction and data locks can be flash cleared separately.

— SRAM features include the following:

– I/O devices access SRAM regions by marking transactions as snoopable (global).

– Regions can reside at any aligned location in the memory map.

– Byte-accessible ECC is protected using read-modify-write transaction accesses for

smaller-than-cache-line accesses.

• Address translation and mapping unit (ATMU)

— Eight local access windows define mapping within local 36-bit address space.

— Inbound and outbound ATMUs map to larger external address spaces.

– Three inbound windows plus a configuration window on PCI and PCI Express

– Four outbound windows plus default translation for PCI and PCI Express

• DDR/DDR2 memory controller

— Programmable timing supporting DDR and DDR2 SDRAM

— 64-bit data interface

MPC8533E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

Recommended Resources

Asynchronous motor protection circuit composed of photoelectric coupler

XTR100 simple circuit diagram

Dual power supply voltage regulator circuit diagram

IF amplifier circuit

Color TV remote control 30

High-voltage rectifier circuit of side-heated rectifier tube

Ask a question about the interrupt interface setting of C8051f series: In C8051f020, after assigning ports to INT0 and INT1, what else do I need to set in the program besides setting XBR1? Thank you...; naphu Embedded System

I would like to ask some questions about 2440 nand flash driver: [code]//Today I looked at some flash driver codes and found some of them puzzling. //Platform description 2440+64M nand flash ----------------------------------------------- /* Write sector function @...; cocalli Embedded System

Newbie asks for advice on GPS chip selection: This is my first time using GPS and I don't know anything about it. I want to use it for remote meter reading concentrator. Can you please tell me how to choose it and what details should I pay attent...; wyygmer MCU

An easy-to-understand microcontroller tutorial: Register first, there will be an introduction after registration, and you will see more things after registration, including teaching materials and experiments. I think it is quite Good, now share. Th...; rain MCU

Cosmic: I downloaded CosMIC for STM8 but it can't simulate. Is it because I don't have a license?I applied for a free license from Cosmic, but why didn't they give it to me?...; heyong stm32/stm8

If you want to make money, play with it: a review of year-end bonuses in various countries: Wall Street is entering the bank bonus season this week. Many US financial institutions are preparing to issue huge year-end bonuses, and the amount is expected to be among the top bonuses in the hist...; fish001 Talking

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components