32C408B
4 Megabit (512K x 8-Bit) SRAM
A13
A0
A1
A2
A3
A4
CS
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
WE
A5
A6
A7
A8
A9
1
36
NC
A18
A17
A16
A15
OE
I/O8
I/O7
A12
A11
A10
A9
A8
A7
A6
A5
A4
ROW
DECODER
MEMORY MATRIX
1024 ROWS x 4096 COLUMNS
DQ0
32C408B
Vss
Vcc
I/O6
I/O5
A14
A13
A12
A11
A10
CS
DQ7
COLUMN I/O
INPUT
DATA
CONTROL
A18
A17
COLUMN DECODER
A16
A15
A14
A3
A2
A1
A0
DQ0
Memory
WE
OE
DQ7
18
19
NC
Logic Diagram
F
EATURES
:
• 512k x 8-bit CMOS architecture
• R
AD
-P
AK
® technology hardened against natural space radi-
ation
• Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Single event effect:
- SEL
TH
: > 68 MeV/mg/cm
2
- SEU
TH
: < 3MeV/mg/cm
2
- SEU saturated cross section: 6E-9 cm
2
/bit
• Package:
-36 pin R
AD
-P
AK
® flat pack
• Fast propagation time:
-20, 25, 30 ns maximum access time
• Single 5V + 10% power supply
• Low power dissipation:
- Standby: 60mA (TTL); 10mA (CMOS)
- Operating: 180 mA (20 ns); 170 mA (25 ns); 160 mA (30
ns)
• TTL compatible inputs and outputs
• Fully static operation
- No clock or refresh required
• Three state outputs
D
ESCRIPTION
:
DDC’s
32C408B high-speed 4 Megabit SRAM
microcircuit features a greater than 100 krad (Si) total dose
tolerance, depending upon space mission. Using R
AD
-P
AK
®
packaging technology, the 32C408B realizes higher density,
higher performance and lower power consumption, and is well
suited for high-speed system application. Its fully static design
eliminates the need for external clocks, while the CMOS cir-
cuitry reduces power consumption and provides higher reli-
ability. The 32C408B is equipped with eight common input/
output lines, chip select and output enable, allowing for
greater system flexibility and eliminating bus contention.
DDC's
patented R
AD
-P
AK
packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. In a GEO orbit, R
AD
-P
AK
can provides true greater than
100 krad (Si) total radiation dose tolerance; dependent upon
space mission. The patented radiation-hardened R
AD
-P
AK
technology incorporates radiation shielding in the microcircuit
package. It eliminates the need for box shielding while provid-
ing the required radiation shielding for a lifetime in orbit or a
space mission. This product is available with packaging and
screening up to Class S.
05.02.02 Rev 7
All data sheets are subject to change without notice
1
(631) 567-5600 - www.ddc-web.com
©2016 Data Device Corporation
All rights reserved.
4 Megabit (512K x 8-Bit) SRAM
T
ABLE
1. 32C408B A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
S
YMBOL
V
IN
, V
OUT
V
CC
P
D
T
S
T
A
M
IN
-0.5
-0.5
--
-65
-55
32C408B
M
AX
V
CC
+0.5
7.0
1.0
+150
+125
U
NIT
V
V
W
°
C
°
C
T
ABLE
2. 32C408B R
ECOMMENDED
O
PERATING
C
ONDITIONS
P
ARAMETER
Supply Voltage
Ground
Input High Voltage
1
Input Low Voltage
2
Thermal Impedance
1. V
IH
(max) = V
CC
+ 2.0V ac(pulse width < 10ns) for I < 20mA.
2. V
IL
(min) = -2.0V ac(pulse width < 10ns) for I < 20mA.
S
YMBOL
V
CC
V
SS
V
IH
V
IL
M
IN
4.5
0
2.2
-0.5
--
M
AX
5.5
0
V
CC
+0.5
0.8
0.63
U
NIT
V
V
V
V
°C/W
Memory
Θ
JC
T
ABLE
3. 32C408B DC E
LECTRICAL
C
HARACTERISTICS
(V
CC
=5V +/- 10%, T
A
= -55
TO
+1‘25C, U
NLESS
O
TERWISE
S
PECIFIED
P
ARAMETER
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
C
ONDITION
V
IN
= V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
,
V
OUT
=V
SS
to V
CC
I
OL
= 8mA
I
OH
= -4mA
S
YMBOL
I
LI
I
LO
V
OL
V
OH
I
CC
S
UBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
--
--
--
I
SB
I
SB1
C
IN
C
I/O
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
--
--
--
--
--
--
--
--
M
IN
-2
-2
--
2.4
--
180
170
160
60
10
7
8
pF
pF
mA
T
YP
--
--
--
M
AX
2
2
0.4
--
U
NIT
µA
µA
V
V
mA
Average Operating Cur-
Min cycle, 100% Duty, CS=V
IL
,
I
OUT
=0mA, V
IN
= V
IH
or V
IL
rent
-20
-25
-30
Standby Power Supply
Current
Input Capacitance
1
Output Capacitance
1
1. Guaranteed by Design
CS = V
IH
f = 0MHz, CS > V
CC
- 02V, V
IN
>
V
CC
- 0.2V or V
IN
< 0.2V
V
IN
= 0V, f = 1MHz, T
A
= 25 °C.
V
I/O
= 0V
05.02.02 Rev 7
All data sheets are subject to change without notice
2
©2016 Data Device Corporation
All rights reserved.
4 Megabit (512K x 8-Bit) SRAM
T
ABLE
4. 32C408B AC C
HARACTERISTICS FOR
R
EAD
C
YCLE
(V
CC
=5V +/- 10%, T
A
= -55
TO
+1‘25C, U
NLESS
O
TERWISE
S
PECIFIED
P
ARAMETER
Read Cycle Time
-20
-25
-30
Address Access Time
-20
-25
-30
Chip Select Access Time
-20
-25
-30
Output Enable to Output Valid
-20
-25
-30
Chip Select to Output in Low-Z
-20
-25
-30
Output Enable to Output in Low-Z
-20
-25
-30
Chip Deselect to Output in High-Z
-20
-25
-30
Output Disable to Output in High-Z
-20
-25
-30
Output Hold from Address Change
-20
-25
-30
Chip Select to Power Up Time
-20
-25
-30
Chip Select to Power Down Time
-20
-25
-30
S
YMBOL
t
RC
S
UBGROUPS
9, 10, 11
20
25
30
t
AA
9, 10, 11
--
--
--
t
CO
9, 10, 11
--
--
--
t
OE
9, 10, 11
--
--
--
t
LZ
9, 10, 11
--
--
--
t
OLZ
9, 10, 11
--
--
--
t
HZ
9, 10, 11
--
--
--
t
OHZ
9, 10, 11
--
--
--
t
OH
9, 10, 11
3
5
5
t
PU
9, 10, 11
--
--
--
t
PD
9, 10, 11
--
--
--
10
15
20
0
0
0
--
--
--
5
6
8
5
6
8
0
0
0
3
3
3
--
--
--
--
--
--
--
--
--
--
--
--
M
IN
T
YP
32C408B
M
AX
--
--
--
ns
20
25
30
ns
20
25
30
10
12
14
--
--
--
ns
--
--
--
ns
--
--
--
ns
--
--
--
ns
--
--
--
ns
--
--
--
ns
--
--
--
ns
U
NIT
ns
Memory
ns
05.02.02 Rev 7
All data sheets are subject to change without notice
3
©2016 Data Device Corporation
All rights reserved.
4 Megabit (512K x 8-Bit) SRAM
T
ABLE
5. 32408B F
UNCTIONAL
D
ESCRIPTION 1
CS
H
L
L
L
1. X = don’t care.
WE
X
H
H
L
OE
X
H
L
X
M
ODE
Not Select
Output Disable
Read
Write
I/O P
IN
High-Z
High-Z
D
OUT
D
IN
32C408B
S
UPPLY
C
URRENT
I
SB
, I
SB1
I
CC
I
CC
I
CC
T
ABLE
6. 32C408B AC C
HARACTERISTICS FOR
W
RITE
C
YCLE
(V
CC
=5V +/- 10%, T
A
= -55
TO
+1‘25C, U
NLESS
O
TERWISE
S
PECIFIED
P
ARAMETER
Write Cycle Time
-20
-25
-30
Chip Select to End of Write
-20
-25
-30
Address Setup Time
-20
-25
-30
Address Valid to End of Write
-20
-25
-30
Write Pulse Width (OE High)
-20
-25
-30
Write Recovery Time
-20
-25
-30
Write to Output in High-Z
-20
-25
-30
S
YMBOL
t
WC
S
UBGROUPS
9, 10, 11
20
25
30
t
CW
9, 10, 11
14
15
17
t
AS
9, 10, 11
0
0
0
t
AW
9, 10, 11
14
15
17
t
WP
9, 10, 11
14
15
17
t
WR
9, 10, 11
0
0
0
t
WHZ
9, 10, 11
--
--
--
5
5
6
--
--
--
--
--
--
--
--
--
ns
--
--
--
--
--
--
ns
--
--
--
--
--
--
ns
--
--
--
--
--
--
ns
--
--
--
--
--
--
ns
--
--
--
--
--
--
ns
M
IN
T
YP
M
AX
U
NIT
ns
Memory
05.02.02 Rev 7
All data sheets are subject to change without notice
4
©2016 Data Device Corporation
All rights reserved.
4 Megabit (512K x 8-Bit) SRAM
T
ABLE
6. 32C408B AC C
HARACTERISTICS FOR
W
RITE
C
YCLE
(V
CC
=5V +/- 10%, T
A
= -55
TO
+1‘25C, U
NLESS
O
TERWISE
S
PECIFIED
P
ARAMETER
Write Pulse Width(OE Low)
-20
-25
-30
Data to Write Time Overlap
-20
-25
-30
End Write to Output Low-Z 1
-20
-25
-30
Data Hold from Write Time
-20
-25
-30
S
YMBOL
t
WP1
S
UBGROUPS
9, 10, 11
--
--
--
t
DW
9, 10, 11
9
10
11
tOW
9, 10, 11
--
--
--
t
DH
9, 10, 11
0
0
0
--
--
--
6
7
8
--
--
--
20
25
30
M
IN
T
YP
32C408B
M
AX
--
--
--
ns
--
--
--
ns
--
--
--
ns
--
--
--
U
NIT
ns
Memory
F
IGURE
1. T
IMING
W
AVEFORM OF
W
RITE
C
YCLE
(1) (OE C
LOCK
)
05.02.02 Rev 7
All data sheets are subject to change without notice
5
©2016 Data Device Corporation
All rights reserved.
京公网安备 11010802033920号
EEWORLD
