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X1G004501005211

Description
CMOS Output Clock Oscillator,
CategoryPassive components    oscillator   
File Size233KB,5 Pages
ManufacturerSeiko Epson Corporation
Environmental Compliance
Download Datasheet Parametric View All

X1G004501005211 Overview

CMOS Output Clock Oscillator,

X1G004501005211 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerSeiko Epson Corporation
Reach Compliance Codeunknown
Other featuresSTANDBY; ENABLE/DISABLE FUNCTION; TR, 10 INCH
maximum descent time5 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
Installation featuresSURFACE MOUNT
Nominal operating frequency22.1184 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS
Output load50 pF
physical size7.0mm x 5.0mm x 1.3mm
longest rise time5 ns
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
maximum symmetry60/40 %
Clock OSC
SG7050CCN
SG7050CCN 22.118400 MHz HJGA
Product name
Product Number / Ordering code
X1G0045010052xx
Please refer to the 8.Packing information about xx (last 2 digits)
Output waveform CMOS
Pb free / Complies with EU RoHS directive
Reference weight Typ. 147 mg
1.Absolute maximum ratings
Parameter
Symbol
Maximum supply voltage
Storage temperature
Input voltage
Min.
-0.3
-40
-0.5
Typ.
-
-
-
Max.
+7
+125
Vcc+0.5
Unit
V
ºC
V
Conditions / Remarks
-
Storage as single product
OE terminal
Vcc-GND
T_stg
Vin
2.Specifications(characteristics)
Parameter
Symbol
Output frequency
Supply voltage
Operating temperature
Frequency tolerance
Current consumption
Stand-by current
Disable current
Symmetry
Output voltage
Output load condition
Input voltage
Min.
4.5
-40
-50
-
-
-
40
Vcc-0.4
-
-
0.8Vcc
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-5
-
Typ.
22.118400
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
TBD
TBD
TBD
-
TBD
-
TBD
TBD
TBD
TBD
TBD
TBD
-
-
Max.
5.5
+85
50
20
-
10.0
60
-
0.4
50
-
0.2Vcc
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
5
-
Unit
MHz
V
ºC
x10
-6
mA
µA
mA
%
Conditions / Remarks
-
-
T_use
No load condition
-
OE = GND
50% Vcc Level L_CMOS=<50pF
-
-
f0
Vcc
T_use
f_tol
Icc
I_std
I_dis
SYM
V
OH
V
OL
L_CMOS
V
IH
V
IL
t
r
tf
t_str
t
DJ
t
RJ
t
RMS
t
p-p
t
acc
pF
CMOS Load
OE terminal
OE terminal
0.2Vcc to 0.8Vcc Level, L_CMOS=50pF
0.2Vcc to 0.8Vcc Level, L_CMOS=50pF
t = 0 at 0.9Vcc
Deterministic Jitter
Random Jitter
δ(RMS of total distribution)
Peak to Peak
Accumulated Jitter(δ) n=2 to 50000
cycles
Off set Frequency: 12kHz to 20MHz
Rise time
Fall time
Start-up time
Jitter
ns
ns
ms
ps
ps
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
x10
-6
Phase jitter
Phase noise
t
PJ
L(f)
Off set 1Hz
Off set 10Hz
Off set 100Hz Vcc=3.3V
Off set 1kHz
Off set 10kHz
Off set 100kHz Vcc=3.3V
Off set 1MHz
@+25ºC first year
-
Frequency aging
f_age
1 Page

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