SPP3401B
P-Channel Enhancement Mode MOSFET
DESCRIPTION
The SPP3401B is the P-Channel logic enhancement
mode power field effect transistors are produced using
high cell density , DMOS trench technology.
This high density process is especially tailored to
minimize on-state resistance.
These devices are particularly suited for low voltage
application such as cellular phone and notebook
computer power management and other battery powered
circuits, and low in-line power loss are needed in a very
small outline surface mount package.
FEATURES
-30V/-4.0A,R
DS(ON)
= 70mΩ@V
GS
=- 10V
-30V/-3.2A,R
DS(ON)
= 90mΩ@V
GS
=-4.5V
-30V/-1.2A,R
DS(ON)
= 115mΩ@V
GS
=-2.5V
Super high density cell design for extremely low
R
DS (ON)
Exceptional on-resistance and maximum DC
current capability
SOT-23-3L package design
APPLICATIONS
Power Management in Note book
Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
DSC
LCD Display inverter
PIN CONFIGURATION(SOT-23-3L)
PART MARKING
2009 / 01 / 05
Ver.1
Page 1
SPP3401B
P-Channel Enhancement Mode MOSFET
PIN DESCRIPTION
Pin
1
2
3
ORDERING INFORMATION
Part Number
SPP3401BS23RGB
Package
SOT-23-3L
Part
Marking
A1YW
Symbol
G
S
D
Description
Gate
Source
Drain
※
Week Code : A ~ Z( 1 ~ 26 ) ; a ~ z( 27 ~ 52 )
※
SPP3401BS23RGB : Tape Reel ; Pb – Free; Halogen – Free
ABSOULTE MAXIMUM RATINGS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Drain-Source Voltage
Gate –Source Voltage
Continuous Drain Current(T
J
=150
℃
)
Pulsed Drain Current
Continuous Source Current(Diode Conduction)
Power Dissipation
Operating Junction Temperature
Storage Temperature Range
Thermal Resistance-Junction to Ambient
T
A
=25℃
T
A
=70℃
T
A
=25℃
T
A
=70℃
Symbol
V
DSS
V
GSS
I
D
I
DM
I
S
P
D
T
J
T
STG
R
θJA
Typical
-30
±12
-4.0
-3.2
-15
-1.0
1.25
0.8
150
-55/150
120
Unit
V
V
A
A
A
W
℃
℃
℃
/W
2009 / 01 / 05
Ver.1
Page 2
SPP3401B
P-Channel Enhancement Mode MOSFET
ELECTRICAL CHARACTERISTICS
(T
A
=25
℃
Unless otherwise noted)
Parameter
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate Leakage Current
Zero Gate Voltage Drain Current
On-State Drain Current
Drain-Source On-Resistance
Forward Transconductance
Diode Forward Voltage
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Time
Turn-Off Time
Symbol
Conditions
Min.
Typ
Max.
Unit
V
(BR)DSS
V
GS
=0V,I
D
=-250uA
V
GS(th)
V
DS
=V
GS
,I
D
=-250uA
I
GSS
I
DSS
I
D(on)
R
DS(on)
gfs
V
SD
V
DS
=0V,V
GS
=±12V
V
DS
=-24V,V
GS
=0V
V
DS
=-24V,V
GS
=0V
T
J
=55℃
V
DS
≦-5V,V
GS
=-10V
V
GS
=- 10V,I
D
=-4.0A
V
GS
=-4.5V,I
D
=-3.2A
V
GS
=-2.5V,I
D
=-1.2A
V
DS
=-5.0V,I
D
=-4.0A
I
S
=-1.0A,V
GS
=0V
-30
-0.4
-1.0
±100
-1
-10
-10
0.062
0.080
0.107
10
-0.8
0.070
0.090
0.115
-1.2
V
nA
uA
A
Ω
S
V
Q
g
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
DS
=-15V,V
GS
=-10V
I
D
≡-4.0A
10
1.6
3.0
450
95
55
8
18
nC
V
DS
=-15V,V
GS
=0V
f=1MHz
pF
18
18
50
35
ns
V
DD
=-15V,R
L
=15Ω
I
D
≡-1.0A,V
GEN
=-10V
R
G
=6Ω
8
25
25
2009 / 01 / 05
Ver.1
Page 3
stm32/stm8
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