EEWORLDEEWORLDEEWORLD

Part Number

Search

MT5C1001EC-55/IT

Description
1M x 1 SRAM SRAM MEMORY ARRAY
File Size92KB,13 Pages
ManufacturerAUSTIN
Websitehttp://www.austinsemiconductor.com/
Download Datasheet View All

MT5C1001EC-55/IT Overview

1M x 1 SRAM SRAM MEMORY ARRAY

Austin Semiconductor, Inc.
1M x 1 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-92316
• MIL-STD-883
MT5C1001
Limited Availability
PIN ASSIGNMENT
(Top View)
SRAM
28-Pin DIP (C)
(400 MIL)
A10
A11
A12
A13
A14
A15
NC
A16
A17
A18
A19
Q
WE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A9
A8
A7
A6
A5
A4
NC
A3
A2
A1
A0
D
CE\
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
A10
A11
A12
NC
A13
A14
A15
NC
A16
A17
A18
A19
NC
Q
WE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
NC
A9
A8
A7
A6
A5
A4
A3
NC
A2
NC
A1
A0
D
CE\
FEATURES
High Speed: 20, 25, 35, and 45
Battery Backup: 2V data retention
Low power standby
Single +5V (+10%) Power Supply
Easy memory expansion with CE\ and OE\ options.
All inputs and outputs are TTL compatible
Three-state output
32-Pin Flat Pack (F)
OPTIONS
• Timing
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
• Package(s)
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
MARKING
-20
-25
-35
-45
-55*
-70*
A10
A11
A12
NC
A13
A14
A15
NC
A16
A17
A18
A19
NC
Q
WE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
NC
A9
A8
A7
A6
A5
A4
A3
NC
A2
NC
A1
A0
D
CE\
C
EC
F
DCJ
No. 109
No. 207
No. 303
No. 501
GENERAL DESCRIPTION
The MT5C1001 employs low power, high-performance
silicon-gate CMOS technology. Static design eliminates the
need for external clocks or timing strobes while CMOS circuitry
reduces power consumption and provides for greater
reliability.
For flexibility in high-speed memory applications, ASI
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for addi-
tional flexibility in system design. Writing to these devices is
accomplished when write enable (WE|) and CE\ inputs are both
LOW. Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
The “L” version provides an approximate 50 percent
reduction in CMOS standby current (I
SBC2
) over the standard
version.
All devices operation from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
• Operating Temperature Ranges
Industrial (-40
o
C to +85
o
C)
IT
o
o
Military (-55 C to +125 C)
XT
• 2V data retention/low power
L
*Electrical characteristics identical to those provided for the
45ns access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C1001
Rev. 2.1 06/05
1
Arrow Electronics' award-winning live broadcast starts at 10:00 this morning: Intel FPGA Deep Learning Acceleration Technology
Arrow Electronics' award-winning live broadcast starts at 10:00 this morning: Intel FPGA Deep Learning Acceleration TechnologyClick here to enter the live broadcastLive broadcast time: 10:00-11:30 am,...
EEWORLD社区 FPGA/CPLD
What are the development software of Xilinx?
Dear experts, I would like to ask, what are the software for developing Xilinx? Do they have commands to keep the specified reg from being optimized? ?...
eeleader FPGA/CPLD
Schematic diagram - How does this circuit achieve the self-locking function of the switch?
[i=s]This post was last edited by Plakatu on 2022-3-4 09:08[/i]The circuit is as shown above. Note: The switch is a touch switch and has no self-locking function. *************************************...
普拉卡图 Analog electronics
Power group matching table
[i=s] This post was last edited by dontium on 2015-1-23 13:24 [/i] Resistance matching table...
linming123 Analogue and Mixed Signal
Italian system, garbled characters
Italian system, garbled characters. It should be that the characters are not supported. How can I add supported characters on PB?...
fdds Embedded System
Training notes on DC-DC principles
Training notes on DC-DC principles...
linda_xia Analog electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 714  2694  1148  2297  482  15  55  24  47  10 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号