EEWORLDEEWORLDEEWORLD

Part Number

Search

TCK1A156BT(13)

Description
Tantalum Capacitor, Polarized, Tantalum (dry/solid), 10V, 10% +Tol, 10% -Tol, 15uF, Surface Mount, 1411, CHIP
CategoryPassive components    capacitor   
File Size775KB,6 Pages
ManufacturerCal-Chip Electronics
Environmental Compliance  
Download Datasheet Parametric View All

TCK1A156BT(13) Overview

Tantalum Capacitor, Polarized, Tantalum (dry/solid), 10V, 10% +Tol, 10% -Tol, 15uF, Surface Mount, 1411, CHIP

TCK1A156BT(13) Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerCal-Chip Electronics
package instruction, 1411
Reach Compliance Codecompliant
ECCN codeEAR99
capacitance15 µF
Capacitor typeTANTALUM CAPACITOR
dielectric materialsTANTALUM (DRY/SOLID)
JESD-609 codee3
leakage current0.0015 mA
Manufacturer's serial numberTC
Installation featuresSURFACE MOUNT
negative tolerance10%
Number of terminals2
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package shapeRECTANGULAR PACKAGE
method of packingTR, EMBOSSED PLASTIC, 13 INCH
polarityPOLARIZED
positive tolerance10%
Rated (DC) voltage (URdc)10 V
ripple current183 mA
size code1411
surface mountYES
Delta tangent0.06
Terminal surfaceTin (Sn) - with Nickel (Ni) barrier
Terminal shapeWRAPAROUND
Cal-Chip
Electronics, Incorporated
TC S
ERIES
TC Series Tantalum Solid Electrolytic Capacitors -
Resin Molded Chip Type, Standard Type
TC S
ERIES
:
The TC Series is designed for hybrid circuit
and low profile printed circuit board applications where
inductance is to be minimized, or where substrate space is
at a premium. They can be attached to substrates or circuit
boards by dipsoldering, welding, re-flow soldering or other
conventional methods. These units have the further advan-
tage of being compatible with automatic assembly equip-
ment-minus the problems associated with flexible terminal
lead wires. Our chip tantalums meet all EIA sizes.
R
ATINGS
Capacitance Range:
Tolerance Range:
Rated Voltage:
0.1µF to 220µF
M(±20%), K(±10%)
4V to 50V
I
TEMS
Operating Temperature Range
Maximum Working Temperature
Rated Voltage Range
Capacitance Range
Standard Capacitance Tolerance
Dissipation factor (tan
δ)
Leakage Current
Temperature
Stability
-55°C
+125°C
Temp.
S
PECIFICATIONS
, P
ERFORMANCE
-55°C~+85°C(+125°C)
+85°C (+125°C with derating)
4 VDC ~ 50 VCD
0.1µF ~ 220µF
±20% (M) ±10%(K)
0.1~1.0µF
1.5~100µF
4.0%
6.0%
T
EST
C
ONDITIONS
See Table of Standard Ratings
JIS-C-5102 20°C 120Hz
JIS-C-5102 20°C 120Hz
JIS-C-5102 20°C (5 minutes)
(after rated voltage applied)
Max. Leakage Current
NA
0.125CV or 6.25µA
whichever is greater
Procedure:
1. 20±2°C
2. -55+0 °C Stabilized
-3
3. 20±2°C 15 min.
4. +125+3 °C 2 hrs.
-0
JIS-C-5140 and 5102 85°C
Not more than 0.01CV or
0.5µA, whichever is greater
C
Max
±12%
Max.
±15%
Max. tan
δ
0.1 ~ 1.0µF 6.0%
1.5 ~ 100µF 8.0%
0.1 ~ 1.0µF 6.0%
1.5 ~ 100µF 8.0%
Less than ±5%
Less than
specified value
Surge Voltage
Solder Heat Resistance
Humidity Test
Capacitance Change
Dissipation Factor
Leakage Current
Surge voltage applied, 1000 times with series
resistance of 1000Ω for 30 seconds at intermittent
intervals of 5 minutes
Withstand solder immersion 5 seconds at
260°C or reflow 10 seconds at 260°C
High Temperature Test
Failure Rate at 85°C
Capacitance Change
Dissipation Factor
Leakage Current
Capacitance Change
Dissipation Factor
Leakage Current
Less than ±5%
Less than initial
specified value
Less than ±10%
Less than initial
specified value
JIS-C-5102
at 60°C humidity 90% ~ 95% RH,
500 Hours
JIS-C-5102
85°C, Rated voltage 2000 hours or 125°C
Derating voltage 1000 hours with circuit
resistance of 1Ω/V
1% per 1,000 hours
MTBF 5 X 10
4
Hr.
31
How to set the IO port as open-drain input in Q2?
As the title says, I see that there is an option to automatically compile to open-drain in Q2, but I don't know how to set the IO to open-drain input.Not sure if there is such a function?...
wstt FPGA/CPLD
The Confusion of SDRAM SelfRefresh
I have been learning about SDRAM recently, and some materials say that "when issuing the SelfRefresh command, CKE is set to an invalid state, and the SR mode is entered. At this time, it no longer rel...
mic198 Embedded System
EVC compilation error, please help.
Generating Code... Linking... CVTRES : fatal error CVT1102: out of memory; 42 bytes required LINK : fatal error LNK1123: failure during conversion to COFF: file invalid or corrupt Error executing link...
feifei Embedded System
Lock-in Amplifier Design
I am a newbie, and I want to make a phase-locked amplifier with a reference signal frequency of 5MHz~7MHz. I have checked some information but still have no idea. Can any expert give me some advice?...
tzqqq Analog electronics
stm32f103 uses spi3
[color=#000][backcolor=rgb(209, 217, 226)][font=Simsun]I saw a friend saying that he wanted to use spi3 but the configuration was not working. He uploaded a SPI3 program using the ENC28J60 network mod...
andyzhao365 stm32/stm8
51 Development Board Collector's Edition and the vulgar people's fight 51
This is my own design of 51 single-chip learning development board, which can be used for primary and intermediate single-chip enthusiasts to learn and experiment. It contains almost all the basic exp...
liujianru 51mcu

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1361  1265  2349  186  295  28  26  48  4  6 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号