Standard Products
UT699 32-bit Fault-Tolerant
SPARC
TM
V8/LEON 3FT Processor
Data Sheet
March 28, 2011
FEATURES
Implemented on a 0.25mCMOS technology
Flexible static design allows up to 66MHz clock rate
89 DMIPS throughput via 66MHz base clock frequency
Internally configured clock network
On-board programmable timers and interrupt controllers
High-performance fully pipelined IEEE-754 FPU
Power saving 2.5V core power supply
3.3V I/O compatibility
Hardened-by-design flip-flops and memory cells
Separate instruction and data cache architecture
10/100 Base-T Ethernet port for VxWorks development
Integrated PCI 2.2 compatible core
Four integrated multi-protocol SpaceWire nodes with two
supporting the RMAP protocol
Two CAN-compliant 2.0 bus interfaces
Multifunctional memory controller
-40
o
C to +105
o
C temperature range
Operational environment:
- Intrinsic total-dose: 100 krad(Si) and 300 krad(Si)
- SEL Immune >108 MeV-cm
2
/mg
Packaging options:
- 352-pin Ceramic Quad Flatpack, weight 31.5 grams
- 484-pin Ceramic Land Grid, Column Grid and Ball
Grid Array packages
Standard Microcircuit Drawing 5962-08228
- QML Q and Q+
- QML V pending
Applications
- Nuclear power plant controls
- Critical transportation systems
- High-altitude avionics
- Medical electronics
- X-Ray cargo scanning
INTRODUCTION
The UT699 is a pipelined monolithic, high-performance, fault-
tolerant SPARC
TM
V8/LEON 3FT Processor. The UT699
provides a 32-bit master/target PCI interface, including a 16 bit
user I/O interface for off-chip peripherals. A compliant 2.0
AMBA bus interface integrates the on-chip LEON 3FT,
SpaceWire, Ethernet, memory controller, cPCI, CAN bus, and
programmable interrupt peripherals.
The UT699 is SPARC V8 compliant; compilers and kernels for
SPARC V8 can therefore be used industry standard
development tools. A full software development suite is
available including a C/C++ cross-compiler system based on
GCC and the Newlib embedded C-library.
BCC includes a small run-time kernel with interrupt support
and Pthreads library. For multi-threaded applications, a
SPARC
TM
compliant port of the eCos real-time kernel, RTEMS
4.6.5, and VxWorks 6.x is supported.
1
1.0 Introduction
The UT699 LEON 3FT processor is based upon the industry-standard SPARC V8 architecture. The system-on-chip incorporates the
SPARC V8 core and the peripheral blocks indicated below. The core and peripherals communicate internally via the AMBA
(Advanced Microcontroller Bus Architecture) backplane. This bus is comprised of the AHB (Advanced High-speed Bus) which is
used for high-speed data transfer, and the APB (Advanced Peripheral Bus) which is used for low-speed data transfer.
IEEE754
FPU
MUL/DIV
LEON 3FT
2x4K
D-cache
2x4K
I-cache
Debug
Support Unit
Serial/JTAG
Debug Link
4x SpW
PCI
Bridge
CAN-2.0
MMU
AHB interface
AHB Ctrl
Memory
Controller
AMBA AHB
AMBA APB
UART
8/32-bits memory bus
Timers
IrqCtrl
I/O port
Ethernet
MAC
AHB/APB
Bridge
512 MB
PROM
512 MB
I/O
Up t o1GB
SRAM
Up to 1GB
SDRAM
Figure 1. UT699 Functional Block Diagram
The LEON 3FT architecture includes the following peripheral blocks:
• LEON3 SPARC V8 integer unit with 8kB instruction cache and 8kB of data cache
• IEEE-754 floating point unit
• Debug support unit
• UART and JTAG debug links
• 8/16/32-bit memory controller with EDAC for external PROM and SRAM
• 32-bit SDRAM controller with EDAC for external SDRAM
• Timer unit with three 32-bit timers and watchdog
• Interrupt controller for 15 interrupts in two priority levels
• 16-bit general purpose I/O port (GPIO) which can be used as external interrupt sources
• AMBA AHB status register
• Up to four SpaceWire links with RMAP on channels 3and 4
• Up to two CAN controllers
• Ethernet with support for MII
• cPCI interface with 8-channel arbiter
2
Pin Number
Pin Name
ADDR[10]
ADDR[11]
ADDR[12]
ADDR[13]
ADDR[14]
ADDR[15]
ADDR[16]
ADDR[17]
ADDR[18]
ADDR[19]
ADDR[20]
ADDR[21]
ADDR[22]
ADDR[23]
ADDR[24]
ADDR[25]
ADDR[26]
ADDR[27]
Direction
352 CQFP
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
16
17
18
19
21
22
23
24
26
27
28
29
31
32
33
34
38
39
484 CLGA
AB6
W8
AB7
Y8
AA8
W9
AB8
Y9
W10
AB9
Y10
AA9
W11
AA10
Y11
AB10
AB11
AA11
Reset
Value
low
low
low
low
low
low
low
low
low
low
low
low
low
low
low
low
low
low
Description
Bit 10 of the address bus
Bit 11 of the address bus
Bit 12 of the address bus
Bit 13 of the address bus
Bit 14 of the address bus
Bit 15 of the address bus
Bit 16 of the address bus
Bit 17 of the address bus
Bit 18 of the address bus
Bit 19 of the address bus
Bit 20 of the address bus
Bit 21 of the address bus
Bit 22 of the address bus
Bit 23 of the address bus
Bit 24 of the address bus
Bit 25 of the address bus
Bit 26 of the address bus
Bit 27 of the address bus
2.3 Data Bus
Pin Number
Pin Name
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[4]
DATA[5]
DATA[6]
Direction
352 CQFP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
43
45
46
47
48
50
51
484 CLGA
W12
W13
Y12
AA13
AA12
AB13
W14
Reset
Value
high-z
high-z
high-z
high-z
high-z
high-z
high-z
Description
Bit 0 of the data bus
Bit 1 of the data bus
Bit 2 of the data bus
Bit 3 of the data bus
Bit 4 of the data bus
Bit 5 of the data bus
Bit 6 of the data bus
4
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