FUJITSU SEMICONDUCTOR
DATA SHEET
DS706-00028-2v0-E
32-bit ARM
TM
Cortex
TM
-M3 based Microcontroller
MB9B110R Series
MB9BF112N/R, MB9BF114N/R,
MB9BF115N/R, MB9BF116N/R
DESCRIPTION
The MB9B110R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers
with high-performance and competitive cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and has
peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces ( UART, CSIO,
I
2
C, LIN).
The products which are described in this data sheet are placed into TYPE4 product categories in "FM3
Family PERIPHERAL MANUAL".
Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries.
Copyright©2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2012.6
MB9B110R Series
FEATURES
32-bit ARM Cortex-M3 Core
・
Processor version: r2p1
・
Up to 144MHz Frequency Operation
・
Memory Protection Unit (MPU): improves the reliability of an embedded system
・
Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48
peripheral interrupts and 16 priority levels
・
24-bit System timer (Sys Tick): System timer for OS task management
On-chip Memories
[Flash memory]
These series are based on two independent on-chip Flash memories.
・
MainFlash
・
Up to 512Kbyte
・
Built-in Flash Accelerator System with 16Kbyte trace buffer memory
・
The read access to Flash memory can be achieved without wait cycle up to operation frequency of
72MHz. Even at the operation frequency more than 72MHz, an equivalent access to Flash memory
can be obtained by Flash Accelerator System.
・
Security function for code protection
・
WorkFlash
・
32Kbyte
・
Read cycle
・
4wait-cycle: the operation frequency more than 72MHz
・
2wait-cycle: the operation frequency more than 40MHz, and to 72MHz
・
0wait-cycle: the operation frequency to 40MHz
・
Security function is shared with code protection
[SRAM]
This Series contain a total of up to 64Kbyte on-chip SRAM memories. This is composed of two
independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus or D-code bus of Cortex-M3
core. SRAM1 is connected to System bus.
・
SRAM0: Up to 32 Kbyte
・
SRAM1: Up to 32 Kbyte
External Bus Interface
・
Supports SRAM, NOR and NAND Flash device
・
Up to 8 chip selects
・
8/16-bit Data width
・
Up to 25-bit Address bit
・
Supports Address/Data multiplex
・
Supports external RDY input
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DS706-00028-2v0-E
MB9B110R Series
Multi-function Serial Interface (Max 8channels)
・
4 channels with 16-byte FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3)
・
Operation mode is selectable from the followings for each channel.
・
UART
・
CSIO
・
LIN
・
I
2
C
[UART]
・
Full-duplex double buffer
・
Selection with or without parity supported
・
Built-in dedicated baud rate generator
・
External clock available as a serial clock
・
Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)
・
Various error detect functions available (parity errors, framing errors, and overrun errors)
[CSIO]
・
Full-duplex double buffer
・
Built-in dedicated baud rate generator
・
Overrun error detect function available
[LIN]
・
LIN protocol Rev.2.1 supported
・
Full-duplex double buffer
・
Master/Slave mode supported
・
LIN break field generate (can be changed 13 to 16-bit length)
・
LIN break delimiter generate (can be changed 1 to 4-bit length)
・
Various error detect functions available (parity errors, framing errors, and overrun errors)
[I
2
C]
Standard mode (Max 100kbps) / High-speed mode (Max 400kbps) supported
DMA Controller (8channels)
DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.
・
8 independently configured and operated channels
・
Transfer can be started by software or request from the built-in peripherals
・
Transfer address area: 32bit (4Gbyte)
・
Transfer mode: Block transfer/Burst transfer/Demand transfer
・
Transfer data type: byte/half-word/word
・
Transfer block count: 1 to 16
・
Number of transfers: 1 to 65536
A/D Converter (Max 16channels)
[12-bit A/D Converter]
・
Successive Approximation Register type
・
Built-in 3unit
・
Conversion time: 1.0μs@5V
・
Priority conversion available (priority at 2levels)
・
Scanning conversion mode
・
Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:
4steps)
Base Timer (Max 8channels)
Operation mode is selectable from the followings for each channel.
・
16-bit PWM timer
・
16-bit PPG timer
・
16/32-bit reload timer
・
16/32-bit PWC timer
DS706-00028-2v0-E
3
MB9B110R Series
General Purpose I/O Port
This series can use its pins as general purpose I/O ports when they are not used for external bus or
peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function
can be allocated.
・
Capable of pull-up control per pin
・
Capable of reading pin level directly
・
Built-in the port relocate function
・
Up 103 fast general purpose I/O Ports@120pin Package
・
Some pin is 5V tolerant I/O.
See "PIN DESCRIPTION" to confirm the corresponding pins.
Multi-function Timer (Max 3units)
The Multi-function timer is composed of the following blocks.
・
16-bit free-run timer × 3ch./unit
・
Input capture × 4ch./unit
・
Output compare × 6ch./unit
・
A/D activating compare × 3ch./unit
・
Waveform generator × 3ch./unit
・
16-bit PPG timer × 3ch./unit
The following function can be used to achieve the motor control.
・
PWM signal output function
・
DC chopper waveform output function
・
Dead time function
・
Input capture function
・
A/D convertor activate function
・
DTIF (Motor emergency stop) interrupt function
Real-time clock (RTC)
The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.
・
Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the
week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.
・
Timer interrupt function after set time or each set time.
・
Capable of rewriting the time with continuing the time count.
・
Leap year automatic count is available.
Quadrature Position/Revolution Counter (QPRC) (Max 3channels)
The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position
encoder. Moreover, it is possible to use up/down counter.
・
The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
・
16-bit position counter
・
16-bit revolution counter
・
Two 16-bit compare registers
Dual Timer (32/16-bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down counters.
Operation mode is selectable from the followings for each channel.
・
Free-running
・
Periodic (=Reload)
・
One-shot
4
DS706-00028-2v0-E
MB9B110R Series
Watch Counter
The Watch counter is used for wake up from power saving mode.
Interval timer: up to 64s (Max) @ Sub Clock : 32.768kHz
External Interrupt Controller Unit
・
Up to 16 external interrupt input pin
・
Include one non-maskable interrupt (NMI)
Watchdog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, "Hardware"
watchdog is active in any power saving mode except STOP.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
・
CCITT CRC16 Generator Polynomial: 0x1021
・
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically
selectable.
・
Main Clock
・
Sub Clock
・
High-speed internal CR Clock
・
Low-speed internal CR Clock
・
Main PLL Clock
[Resets]
・
Reset requests from INITX pin
・
Power on reset
・
Software reset
・
Watchdog timers reset
・
Low-voltage detector reset
・
Clock supervisor reset
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.
・
External OSC clock failure (clock stop) is detected, reset is asserted.
・
External OSC frequency anomaly is detected, interrupt or reset is asserted.
: 4MHz to 48MHz
: 32.768kHz
: 4MHz
: 100kHz
DS706-00028-2v0-E
5
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