MP7541B
15 V CMOS
Multiplying 12-Bit
Digital-to-Analog Converter
FEATURES
•
•
•
•
•
•
•
ESD Protection: 2000 V Minimum
Full Four Quadrant Multiplication
Low Glitch Energy
12-Bit Linearity (End-Point)
Guaranteed Monotonic. All Grades. All Temperatures.
TTL/5 V CMOS Compatible
Stable, More Accurate Segmented Architecture
– 2.0 ppm/°C Typ. Gain Error Tempco
– 0.2 ppm/°C Max. Linearity Tempco
– Lowest Sensitivity to Output Amplifier Offset
•
Latch-Up Free
APPLICATIONS
•
•
•
•
•
•
•
•
Industrial Automation
Automatic Test Equipment
Disk Drive Servo Systems
Digital/Synchro Conversion
Programmable Gain Amplifiers
Ratiometric A/D Conversion
Function Generation
Digitally Controlled Filters
GENERAL DESCRIPTION
The MP7541B is a pin-compatible replacement which offers
superior performance in latch-up and ESD protection versus the
comparable 7541 and 7541A. The high ESD protection will re-
duce failures caused by mishandling. These devices are manu-
factured using patented advanced thin film resistors on a double
metal CMOS process which result in ultra stable thin film and su-
perior long life reliability and stability. The MP7541B incorpo-
rates a bit decoding technique yielding lower glitch, higher
speed and excellent accuracy over temperature and time. The
MP7541B’s outstanding features are:
Stability: Both Integral Non-Linearity (INL) and Differential-
Non-Linearity (DNL) are rated at 0.2 ppm/
°
C maximum.
Monotonicity is guaranteed over the entire temperature range.
Gain Temperature Coefficient (TC
GE
) is 2.0 ppm/
°
C typical.
Lower Sensitivity to Output Amplifier Offset: Multiplying
DACs provide an output current into a virtual ground of the out-
put op amp. Additional linearity error caused by the op amp is
reduced by a factor of 3 in the MP7541B versus conventional
R-2R DACs.
SIMPLIFIED BLOCK DIAGRAM
V
DD
40k
80k
“1”
“1”
“1”
“1”
“1”
“1”
40k
40k
80k
R
FB
10k
I
OUT1
V
REF
Switch Drivers
3-7 Decoder
I
OUT2
GND BIT 1 BIT 2
(MSB)
BIT 3
BIT 4
BIT 12
(LSB)
Rev. 2.00
1
MP7541B
ORDERING INFORMATION
Package
Type
Plastic Dip
Plastic Dip
SOIC
SOIC
Ceramic Dip
Ceramic Dip
Temperature
Range
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
–55 to +125
°
C
–55 to +125
°
C
Part No.
MP7541BKN
MP7541BJN
MP7541BKS
MP7541BJS
MP7541BTD*
MP7541BSD*
INL
(LSB)
1/2
1
1/2
1
1/2
1
DNL
(LSB)
1/2
1
1/2
1
1/2
1
Gain Error
(LSB)
5
8
5
8
5
8
*Contact factory for non-compliant military processing
PIN CONFIGURATIONS
See Packaging Section for Package Dimensions
I
OUT1
I
OUT2
GND
(MSB) BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
R
FB
V
REF
V
DD
BIT 12 (LSB)
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
I
OUT1
I
OUT2
GND
(MSB) BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
R
FB
V
REF
V
DD
BIT 12 (LSB)
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
18 Pin PDIP, CDIP (0.300”)
N18, D18
18 Pin SOIC (Jedec, 0.300”)
S18
PIN OUT DEFINITIONS
PIN NO.
1
2
3
4
5
6
7
8
9
NAME
I
OUT1
I
OUT2
GND
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
DESCRIPTION
Current Output 1
Current Output 2
Ground
Data Input Bit 1 (MSB)
Data Input Bit 2
Data Input Bit 3
Data Input Bit 4
Data Input Bit 5
Data Input Bit 6
PIN NO.
10
11
12
13
14
15
16
17
18
NAME
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
V
DD
V
REF
R
FB
DESCRIPTION
Data Input Bit 7
Data Input Bit 8
Data Input Bit 9
Data Input Bit 10
Data Input Bit 11
Data Input Bit 12 (LSB)
Positive Power Supply
Reference Input Voltage
Internal Feedback Resistor
Rev. 2.00
2
MP7541B
ELECTRICAL CHARACTERISTICS
V
DD
= + 15 V, V
REF
= +10 V, I
OUT1
= I
OUT2
= GND = 0 V Unless Otherwise Noted.
Parameter
STATIC PERFORMANCE
1
Resolution (All Grades)
Integral Non-Linearity
(Relative Accuracy)
K, T
J, S
Differential Non-Linearity
K, T
J, S
Gain Error
K, T
J, S
Gain Temperature Coefficient
2
Power Supply Rejection Ratio
N
INL
+1/2
+1
DNL
+1/2
+1
GE
+3
+6
TC
GE
PSRR
5
+50
+5
+8
+2
+100
ppm/°C
ppm/%
∆Gain/∆Temperature
|∆Gain/∆V
DD
|
∆V
DD
= + 5%
Digital Inputs = 0 or 5 V
RL=100Ω, C
EXT
=13pF
t
S
F
T
Egl
t
PD
0.65
1.0
500
60
1.0
µs
mV p-p
nVs
ns
Full scale change
to 1/2 LSB
V
REF
= 20 V p-p
10kHz, Sinewave
00--0 to 11--1
Input Change
From 50% of digital
input to 10% of final
analog output
current
+1/2
+1
LSB
+1/2
+1
LSB
All grades
monotonic over full
temperature range.
Using Internal R
FB
12
12
Bits
LSB
End Point Linearity
Symbol
Min
25
°
C
Typ
Max
Tmin to Tmax
Min
Max
Units
Test Conditions/Comments
Output Leakage Current
DYNAMIC PERFORMANCE
2
Current Settling Time
AC Feedthrough at I
OUT1
Glitch Energy
Propagation Delay
I
LKG
5
+10
+200
nA
REFERENCE INPUT
Input Resistance
DIGITAL INPUTS
Logical “1” Voltage
Logical “0” Voltage
Input Leakage Current
Input Capacitance
2
Data
ANALOG OUTPUTS
2
Output Capacitance
C
OUT1
C
OUT1
C
OUT2
C
OUT2
POWER SUPPLY
3
Functional Voltage Range
2
Supply Current
V
DD
I
DD
4.5
16
1.0
4.5
16
1.0
V
mA
100
50
50
100
pF
pF
pF
pF
DAC all 1’s
DAC all 0’s
DAC all 1’s
DAC all 0’s
V
IH
V
IL
I
INH
, I
INL
C
IN
3.0
2.4
0.8
+1.0
8.0
3.0
0.8
+1.0
8.0
V
V
µA
pF
R
IN
5
10
20
5
20
kΩ
All Digital Inputs = 0 or 5 V
Rev. 2.00
3
MP7541B
ELECTRICAL CHARACTERISTICS (CONT’D)
NOTES:
1
2
3
Full Scale Range (FSR) is 10V for unipolar mode.
Guaranteed but not production tested.
Specified values guarantee functionality. Refer to other parameters for accuracy.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C unless otherwise noted)
1, 2
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +17 V
Digital Input Voltage to GND . . . . GND –0.5 to V
DD
+0.5 V
I
OUT1
, I
OUT2
to GND . . . . . . . . . . . GND –0.5 to V
DD
+0.5 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
V
RFB
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
Storage Temperature . . . . . . . . . . . . . . . . . –65
°
C to +150
°
C
Lead Temperature (Soldering, 10 seconds) . . . . . . +300
°
C
Package Power Dissipation Rating to 75
°
C
CDIP, PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . 850mW
Derates above 75
°
C . . . . . . . . . . . . . . . . . . . . . 11mW/
°
C
NOTES:
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies.
All inputs have protection diodes
which will protect the device from short
transients outside the supplies of less than 20mA for less than 100
µ
s.
APPLICATION NOTES
Refer to Section 8 for Applications Information
PERFORMANCE CHARACTERISTICS
Graph 1. Linearity Error vs.
Digital Input Code
Rev. 2.00
4
MP7541B
18 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
S18
D
18
10
E
H
9
h x 45
°
C
Seating
Plane
e
B
A
1
L
A
α
INCHES
SYMBOL
A
A
1
B
C
D
E
e
H
h
L
MIN
0.097
0.0050
0.014
0.0091
0.451
0.292
MAX
0.104
0.0115
0.019
0.0125
0.461
0.299
MILLIMETERS
MIN
2.464
0.127
0.356
0.231
11.46
7.42
MAX
2.641
0.292
0.483
0.318
11.71
7.59
0.050 BSC
0.400
0.010
0.016
0
°
0.410
0.016
0.035
8
°
1.27 BSC
10.16
0.254
0.406
0
°
10.41
0.406
0.889
8
°
α
Rev. 2.00
5
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