19-4631; Rev 5/09
DS2745
Low-Cost I
2
C Battery Monitor
www.maxim-ic.com
FEATURES
16-Bit Bidirectional Current Measurement
1.56V LSB, ±51.2mV Dynamic Range
104A LSB, ±3.4A Dynamic Range (RSNS =
15m)
Current Accumulation Register Resolution
6.25Vhr LSB, ±204.8mVh Range
0.417mAhr LSB, ±13.65Ah Range
(R
SNS
= 15m)
11-Bit Voltage Measurement
4.88mV LSB, 0V to 4.5V Input Range
11-Bit Temperature Measurement
0.125ºC Resolution, -20ºC to +70ºC
Industry Standard I
2
C Interface
Low Power Consumption:
Active Current:
70A typical, 100A max
Sleep Current:
1A typical, 3A max
PIN CONFIGURATION
SCL
SDA
PIO
SNS
1
2
3
4
8
7
6
5
VDD
VIN
CTG
VSS
MAX
See Table 1 for Ordering Information.
DESCRIPTION
The DS2745 provides current-flow, voltage, and
temperature measurement data to support battery-
capacity monitoring in cost-sensitive applications. The
DS2745 can be mounted on either the host side or
pack side of the application. Current measurement
and coulomb counting is accomplished by monitoring
the voltage drop across an external sense resistor,
voltage measurement is accomplished through a
separate voltage-sense input, and temperature
measurement takes place on-chip. A standard I
2
C
interface with software programmable address gives
the controlling microprocessor access to all data and
status registers inside the DS2745. A low-power sleep
mode state conserves energy when the cell pack is in
storage.
BLOCK DIAGRAM
APPLICATIONS
Cellular
GPS
PDAs
Handheld Products
Table 1. ORDERING INFORMATION
PART
DS2745U+
DS2745U+T&R
MARKING
2745
2745
PIN-PACKAGE
MAX
package
DS2745U+ in Tape-and-Reel
+Denotes a lead(Pb)-free/RoHS-compliant package.
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DS2745 Low-Cost I
2
C Battery Monitor
ABSOLUTE MAXIMUM RATINGS*
Voltage on All Pins Relative to V
SS
Operating Temperature Range
Storage Temperature Range
Soldering Temperature
-0.3V to +6V
-40°C to +85°C
-55°C to +125°C
See IPC/JEDECJ-STD-020A
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(2.5V
V
DD
4.5V; T
A
= 0C to +70C.)
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
Serial Data I/O Pin
Serial Clock Pin
Programmable I/O Pin
VIN Pin
V
DD
SDA
SCL
PIO
V
IN
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
MIN
+2.5
-0.3
-0.3
-0.3
-0.3
TYP
MAX
+4.5
+5.5
+5.5
+5.5
V
DD
+0.3
UNITS
V
V
V
V
V
DC ELECTRICAL CHARACTERISTICS
(2.5V
V
DD
4.5V; T
A
= 0C to +70C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
Active Current
I
ACTIVE
V
DD
= 4.5V
SCL = SDA = V
SS
,
PIO = V
SS
1
1.56
(Note 1)
(Note 2)
-7.82
-1.0
6.25
V
SNS
= V
SS
, (Notes 4, 5)
-188
4.88
0
(Note 12)
-25
0.125
-3
18.6
V
DD
= 3.8V, T
A
= +25°C
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±1
+3
4.992
+25
+0
51.2
+12.5
+1.0
TYP
70
MAX
100
105
3
UNITS
A
Sleep-Mode Current
Current Resolution
Current Full-Scale
Magnitude
Current Offset
Current Gain Error
Accumulated Current
Resolution
Accumulated Current
Offset
Voltage Resolution
Voltage Full-Scale
Voltage Error
Temperature Resolution
Temperature Error
Current Sample Clock
Frequency
Timebase Accuracy
I
SLEEP
I
LSB
I
FS
I
OERR
I
GERR
q
CA
q
OERR
V
LSB
V
FS
V
GERR
T
LSB
T
ERR
f
SAMP
t
ERR
A
V/R
mV/R
V/R
% of
reading
Vh/R
µVh/R
per day
mV
V
mV
°C
ºC
kHz
%
DS2745 Low-Cost I
2
C Battery Monitor
±2
-20°C
≤
T
A
≤
+70°C,
2.5V
≤
V
DD
≤
4.5V
Input Resistance, VIN
Input Logic High:
SCL, SDA, PIO
Input Logic Low:
SCL, SDA, PIO
Output Logic Low:
SDA, PIO
Pulldown Current: SCL,
SDA, PIO
Input Capacitance: SCL,
SDA
SLEEP Timeout
R
IN
V
IH
V
IL
V
OL
I
PD
C
BUS
t
SLEEP
(Note 3)
(Note 1)
(Note 1)
I
OL
= 4mA (Note 1)
0.25
50
2.2
15
1.5
0.6
0.4
±3
M
V
V
V
A
pF
S
2-WIRE INTERFACE TIMING SPECIFICATIONS
(V
DD
= 2.5V to 4.5V, T
A
= -20C to +70C.)
PARAMETER
SYMBOL
CONDITIONS
SCL Clock Frequency
Bus Free Time Between a
STOP and START Condition
Hold Time (Repeated)
START Condition
Low Period of SCL Clock
High Period of SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and
SCL Signals
Fall Time of Both SDA and
SCL Signals
Setup Time for STOP
Condition
Spike Pulse Widths
Suppressed by Input Filter
Capacitive Load for Each
Bus
Line
SCL, SDA Input
Capacitance
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
CB
C
BIN
(Note 10)
(Note 11)
(Note 8, 9)
(Note 8)
(Note 7)
(Note 6)
MIN
0
1.3
0.6
1.3
0.6
0.6
0
100
20 + 0.1C
B
20 + 0.1C
B
TYP
MAX
400
UNITS
KHz
µs
µs
µs
µs
µs
0.9
µs
ns
300
300
ns
ns
µs
0.6
0
50
400
60
ns
pF
pF
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DS2745 Low-Cost I
2
C Battery Monitor
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
All voltages are referenced to V
SS
.
Offset specified after auto-calibration cycle and Current Offset Bias register (COBR) set to 00h.
To properly enter sleep mode, SMOD=1, and the application should hold SDA and SCL low for longer
than the maximum t
SLEEP
.
NBEN = 0, Current Offset Bias Register (COBR) set to 00h, and Accumulation Bias Register (ABR)
set to 00h.
Parameters guaranteed by design.
Timing must be fast enough to prevent the DS2745 from entering sleep mode due to SDA,SCL low
for period >
t
SLEEP
.
f
SCL
must meet the minimum clock low time plus the rise/fall times.
The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the
SCL
signal.
This device internally provides a hold time of at least 100 ns for the SDA signal (referred to the
VIHmin of
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
C
B
total
capacitance of one bus line in pF.
The first voltage measurement after writing the ACR or after device POR is not valid.
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Figure 1. I
2
C Bus Timing Diagram
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DS2745 Low-Cost I
2
C Battery Monitor
PIN DESCRIPTION
PIN
SYMBOL
FUNCTION
Serial Clock Input.
2-Wire clock line. Input only. Connect this pin to the CLOCK
terminal of the battery pack. Pin has an internal pulldown (I
PD
) for sensing
disconnection.
Serial Data Input/Output.
2-Wire data line. Open-drain output driver. Connect this pin
to the DATA terminal of the battery pack. Pin has an internal pulldown (I
PD
) for sensing
disconnection.
General Purpose Input/Output.
Open-drain output driver with input sense. Connect
to a pull up resistor for bidirectional operation.
Sense Resistor Connection.
Connect to the negative terminal of the battery pack.
Connect the sense resistor between V
SS
and SNS.
Device Ground.
Connect to the negative terminal of the Li+ cell outside the cell
protection FETs. Connect the sense resistor between V
SS
and SNS.
Connect to Ground.
Connect to the negative terminal of the Li+ cell outside the cell
protection FETs.
Voltage Sense Input.
The voltage of the Li+ cell is monitored through this input pin.
Power-Supply Input.
Connect to the positive terminal of the Li+ cell through a
decoupling network.
1
2
3
4
5
6
7
8
SCL
SDA
PIO
SNS
V
SS
CTG
VIN
V
DD
Figure 2. BLOCK DIAGRAM
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