19-4596; Rev 4; 5/09
DEMO KIT AVAILABLE
DS3101
Stratum 2/3E/3 Timing Card IC
www.maxim-ic.com
GENERAL DESCRIPTION
When paired with an external TCXO or OCXO, the
DS3101 is a highly integrated central timing and
synchronization solution for SONET/SDH network
elements. With 14 input clocks, the device directly
accepts both line timing from a large number of line
cards and external timing from external DS1/E1 BITS
transceivers. All input clocks are continuously monitored
for frequency accuracy and activity. Any two of the input
clocks can be selected as the references for the two
core DPLLs. The T0 DPLL complies with the Stratum 2,
3E, 3 4E and 4 requirements of GR-1244, GR-253,
G.812 Types I - IV, G.813 and G.8262. From the output
of the core DPLLs, a wide variety of output clock
frequencies and frame pulses can be produced
simultaneously on the 11 output clock pins. Two
DS3101 devices can be configured in a master/slave
arrangement for timing card equipment protection.
The DS3101 registers and I/O pins are backward
compatible with Semtech’s ACS8520 and ACS8530
timing card ICs. The DS3101 is functionally equivalent
to a DS3100 without integrated BITS transceivers.
FEATURES
Synchronization Subsystem for Stratum 2, 3E,
3, 4E, and 4, SMC, SEC and EEC
- Meets Requirements of GR-1244 Stratum 2 - 4,
GR-253, G.812 Types I - IV, G.813 and G.8262
- Stratum 2, 3E or 3 Holdover Accuracy with
Suitable External Oscillator
- Programmable Bandwidth, 0.5mHz to 70Hz
- Hitless Reference Switching on Loss of Input
- Phase Build-Out and Transient Absorption
- Locks To and Generates 125MHz for Gigabit
Synchronous Ethernet per ITU-T G.8261
14 Input Clocks
- 10 CMOS/TTL Inputs Accept 2kHz, 4kHz, and Any
Multiple of 8kHz Up to 125MHz
- Two LVDS/LVPECL/CMOS/TTL Inputs Accept
Nx8kHz Up to 125MHz Plus 155.52MHz
- Two 64kHz Composite Clock Receivers
- Continuous Input Clock Quality Monitoring
- Separate 2/4/8kHz Frame Sync Input
11 Output Clocks
- Five CMOS/TTL Outputs Drive Any Internally
Produced Clock Up to 77.76MHz
- Two LVDS Outputs Each Drive Any Internally
Produced Clock Up to 311.04MHz
- One 64kHz Composite Clock Transmitter
- One 1.544MHz/2.048MHz Output Clock
- Two Sync Pulses: 8kHz and 2kHz
- Output Clock Rates Include 2kHz, 8kHz, NxDS1,
NxDS2, DS3, NxE1, E3, 6.48MHz, 19.44MHz,
38.88 MHz, 51.84MHz, 62.5MHz, 77.76MHz,
125MHz, 155.52MHz, 311.04MHz
Internal Compensation for Master Clock
Oscillator Frequency Accuracy
Processor Interface: 8-Bit Parallel or SPI Serial
1.8V Operation with 3.3V I/O (5V Tolerant)
APPLICATIONS
SONET/SDH ADMs, MSPPs, and MSSPs
Digital Cross-Connects
DSLAMs
Service Provider Routers
FUNCTIONAL DIAGRAM
TIMING FROM
LINE CARDS AND
BITS/SSU RECEIVERS
14
(VARIOUS RATES)
DS3101
SONET/SDH
SYNCHRONIZATION
IC
11
TIMING TO
LINE CARDS AND
BITS/SSU TRANSMITTERS
(VARIOUS RATES)
ORDERING INFORMATION
LOCAL TCXO
OR OCXO
PART
DS3101GN
DS3101GN+
CONTROL STATUS
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
256 CSBGA (17mm)
2
256 CSBGA (17mm)
2
+Denotes
a lead(Pb)-free/RoHS-compliant package.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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DS3101
TABLE OF CONTENTS
1. STANDARDS COMPLIANCE ................................................................................................6
2. BLOCK DIAGRAM.................................................................................................................7
3. APPLICATION EXAMPLE .....................................................................................................8
4. DETAILED DESCRIPTION ....................................................................................................8
5. DETAILED FEATURES .......................................................................................................10
5.1
5.2
5.3
5.4
5.5
5.6
5.7
T0 DPLL F
EATURES
....................................................................................................................10
T4 DPLL F
EATURES
....................................................................................................................10
I
NPUT
C
LOCK
F
EATURES
..............................................................................................................10
O
UTPUT
C
LOCK
F
EATURES
..........................................................................................................11
R
EDUNDANCY
F
EATURES
.............................................................................................................11
C
OMPOSITE
C
LOCK
I/O F
EATURES
...............................................................................................11
G
ENERAL
F
EATURES
...................................................................................................................11
6. PIN DESCRIPTIONS............................................................................................................12
7. FUNCTIONAL DESCRIPTION .............................................................................................18
7.1
7.2
7.3
7.4
7.5
O
VERVIEW
...................................................................................................................................18
D
EVICE
I
DENTIFICATION AND
P
ROTECTION
....................................................................................19
L
OCAL
O
SCILLATOR AND
M
ASTER
C
LOCK
C
ONFIGURATION
...........................................................19
I
NPUT
C
LOCK
C
ONFIGURATION
.....................................................................................................20
7.4.1
7.4.2
7.5.1
7.5.2
7.5.3
7.5.4
Signal Format Configuration......................................................................................................... 20
Frequency Configuration .............................................................................................................. 22
Frequency Monitoring................................................................................................................... 23
Activity Monitoring ........................................................................................................................ 23
Selected Reference Activity Monitoring........................................................................................ 24
Composite Clock Inputs................................................................................................................ 24
Priority Configuration .................................................................................................................... 25
Automatic Selection Algorithm ..................................................................................................... 25
Forced Selection........................................................................................................................... 26
Ultra-Fast Reference Switching.................................................................................................... 26
External Reference Switching Mode ............................................................................................ 26
Output Clock Phase Continuity During Reference Switching....................................................... 27
T0 DPLL State Machine ............................................................................................................... 27
T4 DPLL State Machine ............................................................................................................... 30
Bandwidth..................................................................................................................................... 31
Damping Factor ............................................................................................................................ 32
Phase Detectors ........................................................................................................................... 32
Loss of Phase Lock Detection...................................................................................................... 33
Phase Monitor and Phase Build-Out ............................................................................................ 34
Input to Output Phase Adjustment ............................................................................................... 35
Phase Recalibration ..................................................................................................................... 35
Frequency and Phase Measurement ........................................................................................... 35
Input Wander and Jitter Tolerance ............................................................................................... 36
Jitter and Wander Transfer........................................................................................................... 36
Output Jitter and Wander ............................................................................................................. 37
Signal Format Configuration......................................................................................................... 39
2 of 150
I
NPUT
C
LOCK
Q
UALITY
M
ONITORING
............................................................................................23
7.6
I
NPUT
C
LOCK
P
RIORITY
, S
ELECTION
,
AND
S
WITCHING
..................................................................25
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.7
DPLL A
RCHITECTURE AND
C
ONFIGURATION
.................................................................................27
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
7.7.9
7.7.10
7.7.11
7.7.12
7.7.13
7.8
O
UTPUT
C
LOCK
C
ONFIGURATION
.................................................................................................38
7.8.1
19-4596; Rev 4; 5/09
DS3101
7.8.2
Frequency Configuration .............................................................................................................. 39
Master-Slave Pin Feature............................................................................................................. 49
Master-Slave Output Clock Phase Alignment .............................................................................. 49
Master-Slave Frame and Multiframe Alignment with the SYNC2K Pin........................................ 50
7.9
E
QUIPMENT
R
EDUNDANCY
C
ONFIGURATION
.................................................................................48
7.9.1
7.9.2
7.9.3
7.10 C
OMPOSITE
C
LOCK
R
ECEIVERS AND
T
RANSMITTER
......................................................................52
7.10.1 IC1 and IC2 Receivers ................................................................................................................. 53
7.10.2 OC8 Transmitter ........................................................................................................................... 53
7.11 M
ICROPROCESSOR
I
NTERFACES
..................................................................................................55
7.11.1 Parallel Interface Modes............................................................................................................... 55
7.11.2 SPI Interface Mode....................................................................................................................... 55
7.12 R
ESET
L
OGIC
..............................................................................................................................57
7.13 P
OWER
-S
UPPLY
C
ONSIDERATIONS
..............................................................................................58
7.14 I
NITIALIZATION
.............................................................................................................................58
8. REGISTER DESCRIPTIONS ...............................................................................................59
8.1
8.2
8.3
8.4
9.1
9.2
9.3
9.4
10.1
10.2
10.3
10.4
10.5
10.6
S
TATUS
B
ITS
...............................................................................................................................59
C
ONFIGURATION
F
IELDS
..............................................................................................................59
M
ULTIREGISTER
F
IELDS
...............................................................................................................59
R
EGISTER
D
EFINITIONS
...............................................................................................................60
JTAG D
ESCRIPTION
..................................................................................................................125
JTAG TAP C
ONTROLLER
S
TATE
M
ACHINE
D
ESCRIPTION
............................................................126
JTAG I
NSTRUCTION
R
EGISTER AND
I
NSTRUCTIONS
....................................................................128
JTAG T
EST
R
EGISTERS
.............................................................................................................129
DC C
HARACTERISTICS
...............................................................................................................130
I
NPUT
C
LOCK
T
IMING
.................................................................................................................134
O
UTPUT
C
LOCK
T
IMING
.............................................................................................................134
P
ARALLEL
I
NTERFACE
T
IMING
....................................................................................................135
SPI I
NTERFACE
T
IMING
..............................................................................................................138
JTAG I
NTERFACE
T
IMING
...........................................................................................................139
9. JTAG TEST ACCESS PORT AND BOUNDARY SCAN....................................................125
10. ELECTRICAL CHARACTERISTICS..................................................................................130
11. PIN ASSIGNMENTS ..........................................................................................................140
12. PACKAGE INFORMATION ...............................................................................................145
12.1 256-P
IN
CSBGA (17
MM X
17
MM
) ..............................................................................................145
13. THERMAL INFORMATION................................................................................................146
14. GLOSSARY .......................................................................................................................147
15. ACRONYMS AND ABBREVIATIONS ...............................................................................148
16. TRADEMARK ACKNOWLEDGEMENTS ..........................................................................148
17. DATA SHEET REVISION HISTORY..................................................................................149
19-4596; Rev 4; 5/09
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DS3101
LIST OF FIGURES
Figure 2-1. DS3101 Block Diagram ............................................................................................................................. 7
Figure 3-1. Typical Application Example ..................................................................................................................... 8
Figure 7-1. T0 DPLL State Transition Diagram ......................................................................................................... 28
Figure 7-2. T4 DPLL State Transition Diagram ......................................................................................................... 31
Figure 7-3. Typical MTIE for T0 DPLL Output ........................................................................................................... 37
Figure 7-4. Typical TDEV for T0 DPLL Output .......................................................................................................... 38
Figure 7-5. DPLL Block Diagram ............................................................................................................................... 40
Figure 7-6. OC10 8kHz Options ................................................................................................................................ 48
Figure 7-7. GR-378 Composite Clock Pulse Mask.................................................................................................... 54
Figure 7-8. SPI Clock Polarity and Phase Options.................................................................................................... 56
Figure 7-9. SPI Bus Transactions.............................................................................................................................. 57
Figure 9-1. JTAG Block Diagram............................................................................................................................. 125
Figure 9-2. JTAG TAP Controller State Machine .................................................................................................... 127
Figure 10-1. Recommended Termination for LVDS Pins ........................................................................................ 131
Figure 10-2. Recommended Termination for LVPECL Pins.................................................................................... 132
Figure 10-3. Recommended External Components for AMI Composite Clock Pins ............................................... 133
Figure 10-4. Parallel Interface Timing Diagram (Nonmultiplexed) .......................................................................... 136
Figure 10-5. Parallel Interface Timing Diagram (Multiplexed) ................................................................................. 137
Figure 10-6. SPI Interface Timing Diagram ............................................................................................................. 138
Figure 10-7. JTAG Timing Diagram......................................................................................................................... 139
Figure 11-1. DS3101 Pin Assignment—Left Half .................................................................................................... 143
Figure 11-2. DS3101 Pin Assignment—Right Half.................................................................................................. 144
19-4596; Rev 4; 5/09
4 of 150
DS3101
LIST OF TABLES
Table 1-1. Applicable Telecom Standards................................................................................................................... 6
Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 12
Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 13
Table 6-3. Global Pin Descriptions ............................................................................................................................ 14
Table 6-4. Parallel Interface Pin Descriptions ........................................................................................................... 15
Table 6-5. SPI Bus Mode Pin Descriptions ............................................................................................................... 16
Table 6-6. JTAG Interface Pin Descriptions .............................................................................................................. 16
Table 6-7. General-Purpose I/O Pin Descriptions ..................................................................................................... 16
Table 6-8. Power-Supply Pin Descriptions ................................................................................................................ 17
Table 7-1. GR-1244 Stratum 2/3E/3 Stability Requirements..................................................................................... 19
Table 7-2. Input Clock Capabilities ............................................................................................................................ 21
Table 7-3. Locking Frequency Modes ....................................................................................................................... 22
Table 7-4. Default Input Clock Priorities .................................................................................................................... 25
Table 7-5. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 32
Table 7-6. T0 Adaptation for T4 Phase Measurement Mode .................................................................................... 36
Table 7-7. Output Clock Capabilities ......................................................................................................................... 38
Table 7-8. Digital1 and Digital2 Frequencies............................................................................................................. 41
Table 7-9. APLL Frequency to Output Frequencies (T0 and T4) .............................................................................. 42
Table 7-10. T0 APLL Frequency to T0 Path Configuration ....................................................................................... 42
Table 7-11. T4 APLL Frequency to T4 Path Configuration ....................................................................................... 43
Table 7-12. OC1 to OC7 Output Frequency Selection .............................................................................................. 44
Table 7-13. Possible Frequencies for OC1 to OC7 ................................................................................................... 44
Table 7-14. Equipment Redundancy Methodology ................................................................................................... 48
Table 7-15. Composite Clock Variations ................................................................................................................... 52
Table 7-16. GR-378 Composite Clock Interface Specification .................................................................................. 54
Table 7-17. G.703 Synchronization Interfaces Specification..................................................................................... 54
Table 7-18. Microprocessor Interface Modes ............................................................................................................ 55
Table 8-1. Top-Level Memory Map............................................................................................................................ 59
Table 8-2. Register Map ............................................................................................................................................ 60
Table 9-1. JTAG Instruction Codes ......................................................................................................................... 128
Table 9-2. JTAG ID Code ........................................................................................................................................ 129
Table 10-1. Recommended DC Operating Conditions ............................................................................................ 130
Table 10-2. DC Characteristics................................................................................................................................ 130
Table 10-3. CMOS/TTL Pins ................................................................................................................................... 131
Table 10-4. LVDS Pins ............................................................................................................................................ 131
Table 10-5. LVPECL Pins........................................................................................................................................ 132
Table 10-6. AMI Composite Clock Pins ................................................................................................................... 133
Table 10-7. Recommended External Components for Output Clock OC8.............................................................. 133
Table 10-8. Input Clock Timing................................................................................................................................ 134
Table 10-9. Input Clock to Output Clock Delay ....................................................................................................... 134
Table 10-10. Output Clock Phase Alignment, Frame Sync Alignment Mode......................................................... 134
Table 10-11. Parallel Interface Timing..................................................................................................................... 135
Table 10-12. SPI Interface Timing ........................................................................................................................... 138
Table 10-13. JTAG Interface Timing........................................................................................................................ 139
Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 140
Table 13-1. Thermal Properties, Natural Convection .............................................................................................. 146
19-4596; Rev 4; 5/09
5 of 150
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