19-4628; Rev 3; 5/09
DS3105
Line Card Timing IC
General Description
The DS3105 is a low-cost, feature-rich timing IC for
telecom line cards. Typically, the device accepts two
reference clocks from dual redundant system timing
cards. The DS3105 continually monitors both inputs
and performs automatic hitless reference switching if
the primary reference fails. The highly programmable
DS3105 supports numerous input and output
frequencies including frequencies required for
SONET/SDH, Synchronous Ethernet (1G, 10G, and
100Mbps), wireless base stations, and CMTS
systems. PLL bandwidths from 18Hz to 400Hz are
supported, and a wide variety of PLL characteristics
and device features can be configured to meet the
needs of many different applications.
The DS3105 register set is backward compatible with
Semtech’s ACS8525 line card timing IC. The DS3105
pinout is similar but not identical to the ACS8525.
Advanced DPLL Technology
Programmable PLL Bandwidth: 18Hz to 400Hz
Hitless Reference Switching, Automatic or Manual
Holdover on Loss of All Input References
Frequency Conversion Among SONET/SDH,
PDH, Ethernet, Wireless, and CMTS Rates
Two CMOS/TTL Inputs (≤ 125MHz)
Two LVDS/LVPECL/CMOS/TTL (≤ 156.25MHz)
Backup Input (CMOS/TLL) in Case of Complete
Loss of System Timing References
Three Optional Frame-Sync Inputs (CMOS/TTL)
Continuous Input Clock Quality Monitoring
Numerous Input Clock Frequencies Supported
Ethernet xMII: 2.5, 25, 125, 156.25MHz
SONET/SDH: 6.48, N x 19.44, N x 51.84MHz
PDH: N x DS1, N x E1, N x DS2, DS3, E3
Frame Sync: 2kHz, 4kHz, 8kHz
Custom Clock Rates: Any Multiple of 2kHz Up to
131.072MHz, Any Multiple of 8kHz Up to
155.52MHz
One CMOS/TTL Output (≤ 125MHz)
One LVDS/LVPECL Output (≤ 312.50MHz)
Two Optional Frame-Sync Outputs: 2kHz, 8kHz
Numerous Output Clock Frequencies Supported
Ethernet xMII: 2.5, 25, 125, 156.25, 312.5MHz
SONET/SDH: 6.48, N x 19.44, N x 51.84MHz
PDH: N x DS1, N x E1, N x DS2, DS3, E3
Other: 10, 10.24, 13, 30.72MHz
Frame Sync: 2kHz, 8kHz
Custom Clock Rates: Any Multiple of 2kHz Up to
77.76MHz, Any Multiple of 8kHz Up to
311.04MHz, Any Multiple of 10kHz Up to
388.79MHz
Suitable Line Card IC for Stratum 3/3E/4, SMC,
SEC
Internal Compensation for Master Clock Oscillator
SPI™ Processor Interface
1.8V Operation with 3.3V I/O (5V Tolerant)
Industrial Operating Temperature Range
Features
Five Input Clocks
Applications
SONET/SDH, Synchronous Ethernet, PDH, and
Other Line Cards in WAN Equipment Including
MSPPs, Ethernet Switches, Routers, DSLAMs,
and Wireless Base Stations
Two Output Clocks
Ordering Information
PART
DS3105LN
DS3105LN+
TEMP RANGE
-40C to +85C
-40C to +85C
PIN-PACKAGE
64 LQFP
64 LQFP
+Denotes
a lead(Pb)-free/RoHS-compliant package.
General
SPI is a trademark of Motorola, Inc.
Maxim Integrated Products
1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of
any device may be simultaneously available through various sales channels. For information about device errata, go to:
www.maxim-ic.com/errata.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or
visit Maxim’s website at www.maxim-ic.com.
_____________________________________________________________________________________________ DS3105
Table of Contents
1.
2.
3.
4.
5.
5.1
5.2
5.3
5.4
5.5
5.6
6.
7.
7.1
7.2
7.3
7.4
7.5
STANDARDS COMPLIANCE ..........................................................................................................6
APPLICATION EXAMPLE ...............................................................................................................7
BLOCK DIAGRAM ...........................................................................................................................8
DETAILED DESCRIPTION ..............................................................................................................9
DETAILED FEATURES .................................................................................................................10
I
NPUT
C
LOCK
F
EATURES
...............................................................................................................10
T0 DPLL F
EATURES
......................................................................................................................10
T4 DPLL F
EATURES
......................................................................................................................10
O
UTPUT
APLL F
EATURES
.............................................................................................................11
O
UTPUT
C
LOCK
F
EATURES
............................................................................................................11
G
ENERAL
F
EATURES
.....................................................................................................................11
PIN DESCRIPTIONS ......................................................................................................................12
FUNCTIONAL DESCRIPTION .......................................................................................................16
O
VERVIEW
....................................................................................................................................16
D
EVICE
I
DENTIFICATION AND
P
ROTECTION
.....................................................................................17
L
OCAL
O
SCILLATOR AND
M
ASTER
C
LOCK
C
ONFIGURATION
.............................................................17
I
NPUT
C
LOCK
C
ONFIGURATION
......................................................................................................17
Signal Format Configuration ................................................................................................................ 17
Frequency Configuration...................................................................................................................... 18
Frequency Monitoring .......................................................................................................................... 19
Activity Monitoring ................................................................................................................................ 19
Selected Reference Activity Monitoring ............................................................................................... 20
Priority Configuration............................................................................................................................ 20
Automatic Selection Algorithm ............................................................................................................. 21
Forced Selection .................................................................................................................................. 21
Ultra-Fast Reference Switching ........................................................................................................... 22
External Reference Switching Mode.................................................................................................... 22
Output Clock Phase Continuity During Reference Switching .............................................................. 22
T0 DPLL State Machine ....................................................................................................................... 24
T4 DPLL State Machine ....................................................................................................................... 27
Bandwidth ............................................................................................................................................ 27
Damping Factor.................................................................................................................................... 28
Phase Detectors................................................................................................................................... 28
Loss-of-Lock Detection ........................................................................................................................ 29
Phase Build-Out ................................................................................................................................... 29
Input to Output (Manual) Phase Adjustment........................................................................................ 30
Phase Recalibration ............................................................................................................................. 30
Frequency and Phase Measurement................................................................................................... 31
Input Jitter Tolerance ........................................................................................................................... 32
Jitter Transfer ....................................................................................................................................... 32
Output Jitter and Wander ..................................................................................................................... 32
Signal Format Configuration ................................................................................................................ 33
Frequency Configuration...................................................................................................................... 33
Enable and SYNCn Pin Selection........................................................................................................ 42
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7.4.1
7.4.2
7.5.1
7.5.2
7.5.3
I
NPUT
C
LOCK
M
ONITORING
............................................................................................................19
7.6
I
NPUT
C
LOCK
P
RIORITY
, S
ELECTION
,
AND
S
WITCHING
....................................................................20
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.7
DPLL A
RCHITECTURE AND
C
ONFIGURATION
..................................................................................23
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
7.7.9
7.7.10
7.7.11
7.7.12
7.7.13
7.8
7.9
O
UTPUT
C
LOCK
C
ONFIGURATION
...................................................................................................33
F
RAME AND
M
ULTIFRAME
A
LIGNMENT
............................................................................................42
7.8.1
7.8.2
7.9.1
19-4628; Rev 3; 5/09
_____________________________________________________________________________________________ DS3105
7.9.2
7.9.3
7.9.4
7.9.5
7.9.6
7.9.7
Sampling .............................................................................................................................................. 43
Resampling .......................................................................................................................................... 43
Qualification ......................................................................................................................................... 43
Output Clock Alignment ....................................................................................................................... 43
Frame-Sync Monitor............................................................................................................................. 44
Other Configuration Options ................................................................................................................ 44
7.10
7.11
7.12
7.13
8.
8.1
8.2
8.3
8.4
9.
9.1
9.2
9.3
9.4
10.
10.1
10.2
10.3
10.4
10.5
10.6
11.
12.
13.
14.
15.
M
ICROPROCESSOR
I
NTERFACE
..................................................................................................44
R
ESET
L
OGIC
.............................................................................................................................47
P
OWER
-S
UPPLY
C
ONSIDERATIONS
.............................................................................................47
I
NITIALIZATION
............................................................................................................................47
S
TATUS
B
ITS
.................................................................................................................................48
C
ONFIGURATION
F
IELDS
................................................................................................................48
M
ULTIREGISTER
F
IELDS
.................................................................................................................48
R
EGISTER
D
EFINITIONS
.................................................................................................................49
REGISTER DESCRIPTIONS .........................................................................................................48
JTAG TEST ACCESS PORT AND BOUNDARY SCAN .............................................................101
JTAG D
ESCRIPTION
....................................................................................................................101
JTAG TAP C
ONTROLLER
S
TATE
M
ACHINE
D
ESCRIPTION
.............................................................102
JTAG I
NSTRUCTION
R
EGISTER AND
I
NSTRUCTIONS
......................................................................104
JTAG T
EST
R
EGISTERS
..............................................................................................................105
ELECTRICAL CHARACTERISTICS............................................................................................106
DC C
HARACTERISTICS
.............................................................................................................106
I
NPUT
C
LOCK
T
IMING
...............................................................................................................110
O
UTPUT
C
LOCK
T
IMING
............................................................................................................110
SPI I
NTERFACE
T
IMING
............................................................................................................111
JTAG I
NTERFACE
T
IMING
.........................................................................................................113
R
ESET
P
IN
T
IMING
...................................................................................................................114
PIN ASSIGNMENTS ....................................................................................................................115
PACKAGE INFORMATION .........................................................................................................117
THERMAL INFORMATION ..........................................................................................................118
ACRONYMS AND ABBREVIATIONS .........................................................................................119
DATA SHEET REVISION HISTORY............................................................................................120
19-4628; Rev 3; 5/09
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_____________________________________________________________________________________________ DS3105
List of Figures
Figure 2-1. Typical Application Example ..................................................................................................................... 7
Figure 3-1. Block Diagram ........................................................................................................................................... 8
Figure 7-1. DPLL Block Diagram ............................................................................................................................... 23
Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 25
Figure 7-3. FSYNC 8kHz Options.............................................................................................................................. 41
Figure 7-4. SPI Clock Phase Options ........................................................................................................................ 46
Figure 7-5. SPI Bus Transactions.............................................................................................................................. 46
Figure 9-1. JTAG Block Diagram............................................................................................................................. 101
Figure 9-2. JTAG TAP Controller State Machine .................................................................................................... 103
Figure 10-1. Recommended Termination for LVDS Pins ........................................................................................ 108
Figure 10-2. Recommended Termination for LVPECL Signals on LVDS Input Pins .............................................. 108
Figure 10-3. Recommended Termination for LVPECL-Compatible Output Pins .................................................... 109
Figure 10-4. SPI Interface Timing Diagram ............................................................................................................. 112
Figure 10-5. JTAG Timing Diagram......................................................................................................................... 113
Figure 10-6. Reset Pin Timing Diagram .................................................................................................................. 114
Figure 11-1. Pin Assignment Diagram..................................................................................................................... 116
19-4628; Rev 3; 5/09
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_____________________________________________________________________________________________ DS3105
List of Tables
Table 1-1. Applicable Telecom Standards................................................................................................................... 6
Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 12
Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 12
Table 6-3. Global Pin Descriptions ............................................................................................................................ 13
Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 14
Table 6-5. JTAG Interface Pin Descriptions .............................................................................................................. 14
Table 6-6. Power-Supply Pin Descriptions ................................................................................................................ 15
Table 7-1. Input Clock Capabilities ............................................................................................................................ 18
Table 7-2. Locking Frequency Modes ....................................................................................................................... 18
Table 7-3. Default Input Clock Priorities .................................................................................................................... 21
Table 7-4. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 28
Table 7-5. T0 DPLL Adaptation for the T4 DPLL Phase Measurement Mode .......................................................... 32
Table 7-6. Output Clock Capabilities ......................................................................................................................... 33
Table 7-7. Digital1 Frequencies................................................................................................................................. 35
Table 7-8. Digital2 Frequencies................................................................................................................................. 35
Table 7-9. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) .......................................................... 36
Table 7-10. T0 APLL Frequency Configuration ......................................................................................................... 36
Table 7-11. T0 APLL2 Frequency Configuration ....................................................................................................... 36
Table 7-12. T4 APLL Frequency Configuration ......................................................................................................... 37
Table 7-13. OC3 and OC6 Output Frequency Selection ........................................................................................... 37
Table 7-14. Standard Frequencies for Programmable Outputs ................................................................................ 38
Table 7-15. T0CR1.T0FREQ Default Settings .......................................................................................................... 40
Table 7-16. T4CR1.T4FREQ Default Settings .......................................................................................................... 40
Table 7-17. OC6 Default Frequency Configuration ................................................................................................... 40
Table 7-18. OC3 Default Frequency Configuration ................................................................................................... 41
Table 7-19. External Frame-Sync Mode and Source ................................................................................................ 43
Table 8-1. Register Map ............................................................................................................................................ 49
Table 9-1. JTAG Instruction Codes ......................................................................................................................... 104
Table 9-2. JTAG ID Code ........................................................................................................................................ 105
Table 10-1. Recommended DC Operating Conditions ............................................................................................ 106
Table 10-2. DC Characteristics................................................................................................................................ 106
Table 10-3. CMOS/TTL Pins ................................................................................................................................... 107
Table 10-4. LVDS/LVPECL Input Pins .................................................................................................................... 107
Table 10-5. LVDS Output Pins ................................................................................................................................ 107
Table 10-6. LVPECL Level-Compatible Output Pins............................................................................................... 108
Table 10-7. Input Clock Timing................................................................................................................................ 110
Table 10-8. Input Clock to Output Clock Delay ....................................................................................................... 110
Table 10-9. Output Clock Phase Alignment, Frame-Sync Alignment Mode............................................................ 110
Table 10-10. SPI Interface Timing ........................................................................................................................... 111
Table 10-11. JTAG Interface Timing........................................................................................................................ 113
Table 10-12. Reset Pin Timing ................................................................................................................................ 114
Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 115
Table 13-1. LQFP Package Thermal Properties, Natural Convection..................................................................... 118
Table 13-2. LQFP Theta-JA (
JA
) vs. Airflow ........................................................................................................... 118
19-4628; Rev 3; 5/09
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