19-4750; Rev 1; 7/11
DS34S132
32-Port TDM-over-Packet IC
General Description
The IETF PWE3 SAToP/CESoPSN/HDLC-compliant
DS34S132 provides the interworking functions that
are required for translating TDM data streams into
and out of TDM-over-Packet (TDMoP) data streams
for L2TPv3/IP, UDP/IP, MPLS (MFA-8), and Metro
Ethernet (MEF-8) networks while meeting the jitter
and wander timing performance that is required by
the public network (ITU G.823, G.824, and G.8261).
Up to 32 TDM ports can be translated into as many
as 256 individually configurable pseudowires (PWs)
for transmission over a 100/1000Mbps Ethernet port.
Each TDM port’s bit rate can vary from 64Kbps to
2.048Mbps to support T1/E1 or slower TDM rates.
PW interworking for TDM-based serial HDLC data is
also supported. A built-in time-slot assignment (TSA)
circuit provides the ability to combine any group of
time slots (TS) from a single TDM port into a single
PW. The high level of integration provides the perfect
solution for high-density applications to minimize
cost, board space, and time to market.
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♦
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♦
Features
32 Independent TDM Ports with Serial Data,
Clock, and Sync (Data = 64Kbps to 2.048Mbps)
One 100/1000Mbps (MII/GMII) Ethernet MAC
256 Total PWs, 32 PW per TDM Port, with Any
Combination of TDMoP and/or HDLC PWs
PSN Protocols: L2TPv3 or UDP Over IP (IPv4 or
IPv6), Metro Ethernet (MEF-8), or MPLS (MFA-8)
0, 1, or 2 VLAN Tags (IEEE 802.1Q)
Synchronous or Asynchronous TDM Port
Timing
One Clock Recovery Engine per TDM Port with
One Assignable as a Global Reference
Supported Clock Recovery Techniques
Adaptive Clock Recovery
Differential Clock Recovery
Absolute and Differential Timestamps
Independent Receive and Transmit Interfaces
Two Clock Inputs for Direct Transmit Timing
For Structured T1/E1, Each TDM Port Includes
DS0 TSA Block for any Time Slot to Any PW
32 HDLC/CES Engines (256 Total)
With or Without CAS Signaling
For Unstructured, each TDM Port Includes
One HDLC/SAT Engine (32 Total)
Any data rate from 64Kbps to 2.048Mbps
32-Bit or 16-Bit CPU Processor Bus
CPU-Based OAM and Signaling
UDP-specific
“Special” Ethernet Type
Inband VCCV
ARP
MEF OAM
NDP/IPv6
Broadcast DA
DDR SDRAM Interface
Low-Power 1.8V Core, 3.3V I/O, 2.5V SDRAM
♦
Applications
TDM Circuit Emulation Over PSN
TDM Leased-Line Services Over PSN
TDM Over BPON/GPON/EPON
TDM Over Cable
TDM Over Wireless
Cellular Backhaul
Multiservice Over Unified PSN
HDLC-Encapsulated Data Over PSN
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Functional Diagram
CPU Interface
DS34S1328
32 TDM Ports
32 Serial
Clock &
Data
Interfaces
T1/E1
TSA
Circuit
Emulation
& HDLC
Engines
Buffer
Packet
Generator
Packet
Classifier
100/1000
Ethernet
MAC
♦
♦
MII/
GMII
Ordering Information
PART
DS34S132GNA2
DS34S132GNA2+
PORTS TEMP RANGE PIN-PACKAGE
32
32
-40°C to +85°C 676 BGA
-40°C to +85°C 676 BGA
BERT, CAS &
Conditioning
Manager
Adapter
Clock
+Denotes a lead(Pb)-free/RoHS-compliant package.
DDR SDRAM
Interface
Clock Inputs
& Outputs
Maxim Integrated Products 1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, go to:
www.maxim-ic.com/errata.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
DS34S132 DATA SHEET
TABLE OF CONTENTS
Introduction .................................................................................................................................................... 8
Acronyms and Glossary ................................................................................................................................. 9
Applicable Standards ................................................................................................................................... 10
High Level Description ................................................................................................................................. 11
Application Examples ................................................................................................................................... 13
Block Diagram ............................................................................................................................................. 15
Features ...................................................................................................................................................... 16
Pin Descriptions ........................................................................................................................................... 20
8.1 Short Pin Descriptions ........................................................................................................................... 20
8.2 Detailed Pin Descriptions ....................................................................................................................... 22
9
Functional Description.................................................................................................................................. 27
9.1 Connection Types.................................................................................................................................. 29
9.1.1 SAT/CES Payload Connections ..................................................................................................... 29
9.1.2 HDLC Connections ........................................................................................................................ 29
9.1.3 SAT/CES PW-Timing Connections................................................................................................. 30
9.1.4 CPU Connections .......................................................................................................................... 31
9.2 TDM Port Functions ............................................................................................................................... 32
9.2.1 TDM Port Related Input and Output Clocks .................................................................................... 32
9.2.1.1 PW-Timing ............................................................................................................................. 33
9.2.1.1.1 RXP Clock Recovery (RXP PW-Timing) ......................................................................... 34
9.2.1.1.2 TXP PW-Timing ............................................................................................................. 34
9.2.1.2 TDM Port - One Clock and Two Clock Modes......................................................................... 35
9.2.2 TDM Port Interface......................................................................................................................... 35
9.2.2.1 TDM Port Transmit Interface .................................................................................................. 36
9.2.2.2 TDM Port Receive Interface ................................................................................................... 37
9.2.3 TDM Port Structure & Frame Formats ............................................................................................ 37
9.2.4 Timeslot Assignment Block ............................................................................................................ 38
9.2.4.1 TDM CAS to Packet CAS Translation ..................................................................................... 40
9.2.4.2 TSA Block Loopbacks ............................................................................................................ 42
9.2.5 TDM Port Data Processing Engines ............................................................................................... 42
9.2.5.1 HDLC Engine ......................................................................................................................... 43
9.2.5.1.1 SAT/CES Engine............................................................................................................ 44
9.2.5.2 TDM Port Priority.................................................................................................................... 45
9.2.5.3 Jitter Buffer Settings ............................................................................................................... 45
9.2.6 TDM Diagnostic Functions ............................................................................................................. 50
9.2.6.1 TDM Loopback....................................................................................................................... 50
9.2.6.2 TDM BERT ............................................................................................................................ 51
9.3 Packet Processing Functions ................................................................................................................. 53
9.3.1 Ethernet MAC ................................................................................................................................ 53
9.3.1.1 Ethernet Port Diagnostic Functions ........................................................................................ 54
9.3.1.1.1 Ethernet Loopback ......................................................................................................... 54
9.3.1.1.2 Packet BERT ................................................................................................................. 54
9.3.2 RXP Packet Classification .............................................................................................................. 56
9.3.2.1 Generalized Packet Classification .......................................................................................... 56
9.3.2.2 PW (BID and OAM BID) Packet Classification ........................................................................ 57
9.3.2.2.1 UDP Settings ................................................................................................................. 58
9.3.2.2.2 Handling of Packets with a Matching BID or OAM BID .................................................... 58
9.3.2.2.3 L-bit Signaling for RXP PWs ........................................................................................... 59
9.3.2.3 CPU Packet Classification ...................................................................................................... 59
9.3.2.3.1 Packets with Broadcast Ethernet DA (DPC.CR1.DPBTP and DPC.CR1.DPBCP) ........... 60
9.3.2.3.2 Packets with Unknown Ethernet DA (PC.CR7 – PC.CR19 and DPC.CR1.DPS9) ............ 60
9.3.2.3.3 PW Packets with Unknown PW-ID (DPS6) ..................................................................... 60
9.3.2.3.4 MEF OAM Ethernet Type Packets (MOET)..................................................................... 60
9.3.2.3.5 CPU Destination Ethernet Type Packets (CDET and DPS8) ........................................... 60
9.3.2.3.6 ARP Packet with Known IP Destination Address (PC.CR6 – PC.CR8 and DPS3) ........... 60
9.3.2.3.7 ARP Packet with Unknown IP Destination Address (PC.CR6 – PC.CR8 and DPS0) ....... 60
9.3.2.3.8 Packet with Unknown Ethernet Type (DPS2) .................................................................. 60
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DS34S132 DATA SHEET
9.3.2.3.9 IP Packets with Unknown IP Protocol (DPS4) ................................................................. 60
9.3.2.3.10 IP Packet with Unknown IP Destination Address (PC.CR6 – PC.CR16 and DPS1) ......... 60
9.3.2.3.11 “CPU Debug RXP PW Bundle” Setting (RXBDS) ............................................................ 61
9.3.2.3.12 PW Bundle with Unknown UDP Protocol Type (UPVCE and DPS5)................................ 61
9.3.2.3.13 PW Bundle In-band VCCV OAM (RXOICWE and DPS7) ................................................ 61
9.3.2.3.14 PW Bundle with Too Many MPLS Labels (DPS10).......................................................... 61
9.3.2.3.15 PW OAM Bundle - Out-band VCCV OAM Packets (DPS7) ............................................. 61
9.3.3 TXP Packet Generation ................................................................................................................. 61
9.3.3.1 TXP SAT/CES/HDLC/Clock Only PW Packet Generation ....................................................... 62
9.3.3.1.1 L-bit Signaling ................................................................................................................ 63
9.3.3.2 TXP CPU Packet Generation ................................................................................................. 63
9.3.3.3 TXP Packet Scheduling.......................................................................................................... 63
9.3.3.4 TXP Packet Queue Monitoring ............................................................................................... 63
9.4 CPU Packet Interface ............................................................................................................................ 63
9.4.1 RXP CPU Packet Interface ............................................................................................................ 63
9.4.2 TXP CPU Packet Interface ............................................................................................................. 66
9.5 Clock Recovery Functions ..................................................................................................................... 68
9.6 Miscellaneous Global Functions............................................................................................................. 68
9.6.1 Global Resets ................................................................................................................................ 68
9.6.2 Latched Status and Counter Register Reset ................................................................................... 68
9.6.3 Buffer Manager .............................................................................................................................. 68
9.6.3.1 SDRAM Interface ................................................................................................................... 69
9.6.4 CPU Electrical Interconnect ........................................................................................................... 69
9.6.5 Interrupt Hierarchy ......................................................................................................................... 71
10 Device Registers.......................................................................................................................................... 74
10.1 Register Block Address Ranges ............................................................................................................. 74
10.2 Register Address Reference List ............................................................................................................ 75
10.3 Register Definitions................................................................................................................................ 83
10.3.1 Global Registers (G.) ..................................................................................................................... 83
10.3.1.1 Global Configuration Registers (G.) ........................................................................................ 83
10.3.1.2 Global Status Registers (G.)................................................................................................... 86
10.3.1.3 Global Status Register Interrupt Enables (G.) ......................................................................... 88
10.3.2 Bundle Registers (B.) ..................................................................................................................... 89
10.3.2.1 Bundle Reset Registers (B.) ................................................................................................... 89
10.3.2.2 Bundle Data Control Registers (B.)......................................................................................... 90
10.3.2.3 Bundle Data Registers (B.) ..................................................................................................... 91
10.3.2.4 Bundle Status Latch Registers (B.) ......................................................................................... 97
10.3.2.5 Bundle Status Register Interrupt Enables (B.)....................................................................... 100
10.3.3 Jitter Buffer Registers (JB.) .......................................................................................................... 104
10.3.3.1 Jitter Buffer Status Registers (JB.)........................................................................................ 104
10.3.3.2 Jitter Buffer Status Register Interrupt Enables (JB.) .............................................................. 107
10.3.4 Packet Classifier Registers (PC.) ................................................................................................. 110
10.3.4.1 Packet Classifier Configuration Registers (PC.) .................................................................... 110
10.3.4.2 Packet Classifier Status Register Latches (PC.) ................................................................... 113
10.3.4.3 Packet Classifier Status Register Interrupt Enables (PC.) ..................................................... 114
10.3.4.4 Packet Classifier Counter Registers (PC.) ............................................................................ 115
10.3.5 External Memory Interface Registers (EMI.) ................................................................................. 115
10.3.5.1 External Memory Interface Configuration Registers (EMI.) .................................................... 115
10.3.5.2 External Memory Interface Status Registers (EMI.)............................................................... 116
10.3.5.3 External Memory Interface Status Register Interrupt Enables (EMI.) ..................................... 117
10.3.5.4 External Memory DLL/PLL Test Registers (EMI.).................................................................. 118
10.3.6 External Memory Access Registers (EMA.) .................................................................................. 118
10.3.6.1 Write Registers (EMA.)......................................................................................................... 118
10.3.6.2 Read Registers (EMA.) ........................................................................................................ 120
10.3.7 Encap BERT Registers (EB.) ....................................................................................................... 122
10.3.8 Decap BERT Registers (DB.) ....................................................................................................... 124
10.3.9 Miscellaneous Diagnostic Registers (MD.) ................................................................................... 126
10.3.10 Test Registers (TST.)................................................................................................................... 127
10.3.11 Clock Recovery Registers (CR.)................................................................................................... 129
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DS34S132 DATA SHEET
10.3.12 MAC Registers (M.) ..................................................................................................................... 129
10.3.13 TXP SW CAS Registers (TXSCn.) ............................................................................................... 138
10.3.14 Xmt (RXP) SW CAS Registers (RXSCn.) ..................................................................................... 139
10.3.15 TDM Port n Registers (Pn.; n = 0 to 31)........................................................................................ 140
10.3.15.1 Port n Transmit Configuration Registers (Pn.)....................................................................... 140
10.3.15.2 Port n Transmit Status Registers (Pn.) ................................................................................. 142
10.3.15.3 Port n Transmit Status Register Latches (Pn.) ...................................................................... 143
10.3.15.4 Port n Transmit Status Register Interrupt Enables (Pn.) ........................................................ 143
10.3.15.5 Port n Receive Configuration Registers (Pn.)........................................................................ 144
10.3.15.6 Port n Receive Status Registers (Pn.) .................................................................................. 146
10.3.15.7 Port n Receive Status Register Latches (Pn.) ....................................................................... 147
10.3.15.8 Port n Receive Status Register Interrupt Enables (Pn.) ......................................................... 147
10.3.16 Timeslot Assignment Registers (TSAn.m.; “n” = TDM Port n; “m” = Timeslot m) ........................... 147
10.4 Register Guide..................................................................................................................................... 148
10.4.1 Global Packet Settings ................................................................................................................. 149
10.4.2 Bundle and OAM Bundle Settings ................................................................................................ 151
10.4.2.1 SAT Bundle Settings ............................................................................................................ 152
10.4.2.2 CES without CAS Bundle Settings........................................................................................ 153
10.4.2.3 CES with CAS Bundle Settings ............................................................................................ 154
10.4.2.4 Unstructured HDLC Bundle (any Line Rate) Settings ............................................................ 155
10.4.2.5 Structured Nx64 Kb/s HDLC Bundle Settings ....................................................................... 156
10.4.2.6 Structured 16 Kb/s or 56 Kb/s HDLC Bundle Settings ........................................................... 157
10.4.2.7 Clock Only Bundle Settings .................................................................................................. 158
10.4.2.7.1 Combined RXP and TXP (Bidirectional) Clock Only Bundle Settings............................. 158
10.4.2.7.2 RXP (Unidirectional) Clock Only Bundle Settings .......................................................... 159
10.4.2.7.3 TXP (Unidirectional) Clock Only Bundle Settings .......................................................... 160
10.4.2.8 “CPU RXP PW Debug” Bundle Settings ............................................................................... 161
10.4.2.9 In-band VCCV OAM Connection Settings ............................................................................. 162
10.4.2.10 OAM Bundle (Out-band VCCV OAM) Settings...................................................................... 162
10.4.3 Send to CPU Settings .................................................................................................................. 163
10.4.4 TDM Port Settings........................................................................................................................ 163
10.4.5 Status Monitoring ......................................................................................................................... 167
10.4.5.1 Ethernet Port Monitoring....................................................................................................... 167
10.4.5.2 Global Packet Classifier Monitoring Control .......................................................................... 168
10.4.5.3 Global RXP Bundle Monitoring Control ................................................................................. 168
10.4.5.4 Global TXP Packet Queue Monitoring .................................................................................. 168
10.4.5.5 PW Bundle Monitoring.......................................................................................................... 168
10.4.6 SDRAM Settings .......................................................................................................................... 169
11 JTAG Information ....................................................................................................................................... 171
12 DC Electrical Characteristics ...................................................................................................................... 172
13 AC Timing Characteristics .......................................................................................................................... 173
13.1 CPU Interface ...................................................................................................................................... 173
13.2 TDM Interface...................................................................................................................................... 175
13.3 MAC Interface...................................................................................................................................... 177
13.3.1 GMII Interface .............................................................................................................................. 177
13.3.2 MII Interface................................................................................................................................. 177
13.4 DDR SDRAM Timing ........................................................................................................................... 178
14 Pin Assignment .......................................................................................................................................... 180
15 Package Information .................................................................................................................................. 192
16 Thermal Information ................................................................................................................................... 193
17 Data sheet Revision History ....................................................................................................................... 194
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DS34S132 DATA SHEET
LIST OF FIGURES
Figure 5-1. TDMoP in a Metropolitan Packet Switched Network ........................................................................... 13
Figure 5-2. TDMoP in Cellular Backhaul............................................................................................................... 14
Figure 6-1. DS34S132 Functional Block Diagram ................................................................................................. 15
Figure 9-1. S132 Block Diagram .......................................................................................................................... 28
Figure 9-2. RXP/TXP Data Path Directions .......................................................................................................... 28
Figure 9-3. SAT/CES Payload Connection ........................................................................................................... 29
Figure 9-4. Bundle HDLC Connection .................................................................................................................. 29
Figure 9-5. Bundle PW-Timing Connections ......................................................................................................... 30
Figure 9-6. CPU Connections .............................................................................................................................. 31
Figure 9-7. TDM Port Input and Output Clock Overview ....................................................................................... 32
Figure 9-8. Clock Recovery Engine Environment.................................................................................................. 34
Figure 9-9. TXP PW-Timing Environment ............................................................................................................. 34
Figure 9-10. TDM Port #1 Environment ................................................................................................................ 35
Figure 9-11. Logic Detail for a Single TDM Port Interface ..................................................................................... 36
Figure 9-12. T1 ESF CAS to SF CAS Translation Example .................................................................................. 37
Figure 9-13. TSA Block Environment ................................................................................................................... 39
Figure 9-14. HDLC Engine Environment .............................................................................................................. 43
Figure 9-15. SAT/CES Engine Environment ......................................................................................................... 44
Figure 9-16. Bundle Jitter Buffer FIFO.................................................................................................................. 48
Figure 9-17. T1/E1 Port Line Loopback and TDM Port Timeslot Loopback Diagram ............................................. 51
Figure 9-18. T1/E1 Port Bundle Loopback Diagram.............................................................................................. 51
Figure 9-19. TDM Port BERT Diagram ................................................................................................................. 51
Figure 9-20. Ethernet MAC Environment .............................................................................................................. 53
Figure 9-21. Ethernet Port Local Loopback .......................................................................................................... 54
Figure 9-22. Ethernet Port BERT Diagram ........................................................................................................... 55
Figure 9-23. RXP Packet Classifier Environment.................................................................................................. 56
Figure 9-24. TXP Packet Generation Environment ............................................................................................... 61
Figure 9-25. SAT/CES/HDLC/Clock Only PW TXP Header Descriptor.................................................................. 62
Figure 9-26. Stored RXP CPU Packet .................................................................................................................. 64
Figure 9-27. Stored TXP CPU Packet and Header Descriptor .............................................................................. 66
Figure 9-28. Buffer Manager Environment............................................................................................................ 68
Figure 9-29. MPC870 32-bit Bus Interface............................................................................................................ 70
Figure 9-30. MPC8313, Non-multiplexed Bus Interface ........................................................................................ 71
Figure 9-31. MPC8313, Multiplexed Bus Interface ................................................................................................ 71
Figure 9-32. Interrupt Hierarchy Diagram ............................................................................................................. 73
Figure 10-1. Register Guide High Level Diagram................................................................................................ 148
Figure 13-1. MPC870-like processor CPU Interface Write Cycle......................................................................... 174
Figure 13-2. MPC870-like processor CPU Interface Read Cycle ........................................................................ 174
Figure 13-3. MPC8313-like processor CPU Interface Write Cycle....................................................................... 174
Figure 13-4. MPC8313-like processor CPU Interface Read Cycle ...................................................................... 175
Figure 13-5. TDM Port using Single Clock (TCLKO), positive edge timing (RSS = 1, TIES = RIES = 0) .............. 176
Figure 13-6. TDM Port using Two Clock, negative edge timing (RSS = 0, TIES = RIES = 1) ............................... 176
Figure 13-7. GMII Transmit Timing .................................................................................................................... 177
Figure 13-8. GMII Receive Timing ..................................................................................................................... 177
Figure 13-9. MII Transmit Timing ...................................................................................................................... 178
Figure 13-10. MII Receive Timing...................................................................................................................... 178
Figure 13-11. DDR SDRAM Timing .................................................................................................................... 179
Figure 15-1. 676-Ball TEPBGA (56-G6029-001)................................................................................................. 192
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