High Speed LAN Interface Module
ELECTRONICS INC.
EPF8016
• Recommended for 10/100, 100 BX, 155 Mb/s applications •
(requiring 1:1 magnetics)
• Guaranteed to operate with 8 mA DC bias at 70°C •
• Complies with or exceeds IEEE 802.3, 10 BT/100 BX Standards •
Electrical Parameters @ 25° C
OCL
@ 70°C
100 KHz, 0.1 Vrms
8 mA DC Bias
Cable Side
350µH
1-80
MHz
Xmit
-1
•
Insertion Loss
(dB Max.)
80-100
MHz
Xmit
-1
100-150
MHz
Xmit
-3
1-32
MHz
Xmit
-20
Return Loss
(dB Min.)
32-62
MHz
Xmit
-17
62-100
MHz
Xmit
-12
Common Mode Rejection
(dB Min.)
50
MHz
Xmit
-50
100
MHz
Xmit
-45
200
MHz
Xmit
-40
Isolation
: 1500 Vrms •
Impedance
: 100
Ω
•
Rise Time
: 3.0 nS Max. •
Schematic
1
7
No pin 4
2
3
1:1
6
5
Package
Dimensions
A
B
Pin 1 I.D.
PCA
EPF8016
Date Code
Dim.
A
B
C
D
E
F
G
H
I
J
K
(Inches)
Min. Max. Nom.
.790
.190
.355
.700
.015
.100
.018
.008
.065
.150
.810
.210
.375
Typ.
Typ.
Typ.
.125
.021
.012
Typ.
.160
.457
.203
1.65
3.81
.533
.305
Typ.
4.06
(Millimeters)
Min.
Max. Nom.
20.07 20.57.
4.83
5.33
9.02 9.53
17.78 Typ.
.381
Typ.
2.54
Typ.
3.175
C
E
K
I
G
J
H
D
F
PCA ELECTRONICS, INC.
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
CSF8016a Rev. 3
9/30/96
Product performance is limited to specified parameters. Data is subject to change without prior notice.
TEL: (818) 892-0761
FAX: (818) 894-5791
http://www.pcainc.com
High Speed LAN Interface Module
ELECTRONICS INC.
EPF8016
The circuit below is a guideline for interconnecting PCA’s EPF8016 with a typical 100 BX PHY chip for 100 Mb/s applications
over UTP cable. Further details of system design, such as chip pin-out, etc. should be obtained from the specific chip
manufacturer. The package is a minature SIP, built for convenience of dense board designs for both NIC’s and multiport
applications. Each port requires two such devices.
Typical insertion loss of the isolation transformer is 0.5dB. This parameter covers the entire spectrum of the encoded
signals in 100/155 protocols. Under terminated conditions, to transmit a 2V pk-pk signal across the cable, you must adjust
the specific chip preset template control resistors to get at least 2.12V pk-pk across the transmit side input pins.
It is recommended that system designers do not ground the receiver side center tap, via a capacitor. This may worsen
EMI, specifically if the secondary “common mode termination” is pulled to chassis ground as shown.
Pulling unused pins on the RJ45 to chassis via 50
Ω
has been known to suppress unwanted radiation that unused wires
pick up from the immediate environment. Their placement and use are to be considered carefully before a design is
finalized.
The “common mode termination” load of 75
Ω
shown from the center taps of the secondary may be taken to chassis ground
via a suitable cap. This depends upon the user’s design, EMI margin, etc.
It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit
the plane off at least 0.05 inches away from pins of EPF8016 the chip side. There need not be any ground plane beyond
this point.
For best results, the PCB designer should design the outgoing traces preferably to be 50
Ω,
balanced and well coupled to
achieve minimum radiation from these traces.
Typical Application Circuit for 100 BX over UTP
RX+
1
7
6
1
Rcv
75Ω
.01 µƒ
2 kV
2
3
6
RX-
2
RJ45*
5
100BX
PHY
TX+
TX-
1
2
EPF8016
7
6
5
75Ω
.01 µƒ
2 kV
EPF8016
Vcc
Notes : * Pin-outs shown are for DCE configurations : e.g. Hubs, Repeaters
PCA ELECTRONICS, INC.
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
CSF8016b Rev. 3
9/30/96
TEL: (818) 892-0761
FAX: (818) 894-5791
http://www.pcainc.com
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