without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.-
www.issi.com
Rev. A
04/26/2016
1
IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
PIN CONFIGURATIONS
48-Pin mini BGA (6mm x 8mm)
1
2
3
4
5
6
48-Pin mini BGA (6mm x 8mm)
2 CS Option
1
2
3
4
5
6
A
LB#
OE#
A0
A1
A2
NC
A
LB#
OE#
A0
A1
A2
CS2
B
I/O8
UB#
A3
A4
CS#
I/O0
B
I/O8
UB#
A3
A4
CS1#
I/O0
C
I/O9
I/O10
A5
A6
I/O1
I/O2
C
I/O9
I/O10
A5
A6
I/O1
I/O2
D
GND
I/O11
A17
A7
I/O3
VDD
D
GND
I/O11
A17
A7
I/O3
VDD
E
VDD
I/O12
NC
A16
I/O4
GND
E
VDD
I/O12
NC
A16
I/O4
GND
F
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O14
I/O13
A14
A15
I/O5
I/O6
G
I/O15
NC
A12
A13
WE#
I/O7
G
I/O15
NC
A12
A13
WE#
I/O7
H
NC
A8
A9
A10
A11
NC
H
NC
A8
A9
A10
A11
NC
PIN DESCRIPTIONS
A0-A17
I/O0-I/O15
CS1#, CS2
CS#
OE#
WE#
LB#
UB#
NC
V
DD
GND
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control
(I/O0-I/O7)
Upper-byte Control
(I/O8-I/O15)
No Connection
Power
Ground
44-Pin mini TSOP (Type II)
A4
1
2
44
A5
A6
A7
OE#
A3
A2
43
42
41
40
39
38
37
36
35
34
3
4
A1
A0
CS#
I/O0
I/O1
I/O2
5
6
7
8
9
10
11
UB#
LB#
I/O15
I/O14
I/O13
I/O12
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE#
A16
A15
A14
A13
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A8
12
13
14
14
16
17
18
33
32
31
30
29
28
27
26
25
24
19
20
21
22
A9
A10
A11
A12
23
A17
Integrated Silicon Solution, Inc.-
www.issi.com
Rev. A
04/26/2016
2
IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
FUNCTION DESCRIPTION
SRAM is one of random access memories. Each byte or word has an address and can be accessed
randomly. SRAM has three different modes supported. Each function is described below with Truth Table.
Below description is based on the device with 2 CS inputs.
STANDBY MODE
Device enters standby mode when deselected (CS1# HIGH or CS2 LOW or both UB# and LB# are HIGH). The input
and output pins (I/O0-15) are placed in a high impedance state. The current consumption in this mode will be ISB1 or
ISB2. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input LOW. The input
and output pins (I/O0-15) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB#
and LB# enables a byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the
location specified on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written
into the location.
READ MODE
Read operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input HIGH. When
OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB#
and LB# enables a byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB#
being LOW, data from memory appears on I/O8-15.
In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
CS1#
H
X
X
L
L
L
L
L
L
L
L
CS2
X
L
X
H
H
H
H
H
H
H
H
WE#
X
X
X
H
H
H
H
H
L
L
L
OE#
X
X
X
H
H
L
L
L
X
X
X
LB#
X
X
H
L
X
L
H
L
L
H
L
UB#
X
X
H
X
L
H
L
L
H
L
L
I/O0-I/O7
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
I/O8-I/O15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
DIN
VDD Current
ISB2
ICC,ICC1
ICC,ICC1
Write
ICC,ICC1
Note:
1. Truth table for the device with 1 CS input is the same with the above table without CS2 column.
Integrated Silicon Solution, Inc.-
www.issi.com
Rev. A
04/26/2016
3
IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Vter m
V
DD
tStg
P
T
Notes:
1.
Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter
Terminal Voltage with Respect to GND
V
DD
Related to GND
Storage Temperature
Power Dissipation
Value
–0.5 to V
DD
+ 0.5V
–0.3 to 4.0
–65 to +150
1.0
Unit
V
V
C
W
OPERATING RANGE
(1)
Range
Commercial
Industrial
Automotive
Commercial
Industrial
Automotive
Commercial
Industrial
Automotive
Note:
1.
Ambient Temperature
0C to +70C
-40C to +85C
-40C to +125C
0C to +70C
-40C to +85C
-40C to +125C
0C to +70C
-40C to +85C
-40C to +125C
Part Number
~EALL
S
PEED
(max)
55 ns
55 ns
55 ns
45ns
45ns
55ns
35ns
35ns
45ns
VDD(min)
1.65V
1.65V
1.65V
2.2V
2.2V
2.2V
3.135V
3.135V
3.135V
VDD(typ)
1.8V
1.8V
1.8V
3.0V
3.0V
3.0V
3.3V
3.3V
3.3V
VDD(max)
2.2V
2.2V
2.2V
3.6V
3.6V
3.6V
3.465V
3.465V
3.465V
~EBLL
~ECLL
Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization.
PIN CAPACITANCE
(1)
Parameter
Input capacitance
DQ capacitance (IO0–IO15)
Symbol
C
IN
C
I/O
Test Condition
T
A
= 25°C, f = 1 MHz, V
DD
= V
DD
(typ)
Max
6
8
Units
pF
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
THERMAL CHARACTERISTICS
(1)
Parameter
Thermal resistance from junction to ambient (airflow = 1m/s)
Thermal resistance from junction to pins
Thermal resistance from junction to case
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
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