CN80617006042AB/SLBUG datasheet, PDF

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CN80617006042AB/SLBUG: DescriptionRISC Microprocessor, 64-Bit, 1200MHz, CMOS, PBGA1288; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，388 Pages; ManufacturerIntel; Websitehttp://www.intel.com/; Environmental Compliance

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CN80617006042AB/SLBUG Overview

RISC Microprocessor, 64-Bit, 1200MHz, CMOS, PBGA1288

CN80617006042AB/SLBUG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Intel
package instruction	BGA, BGA1288(UNSPEC)
Reach Compliance Code	compliant
bit size	64
Number of terminals	1288
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA1288(UNSPEC)
Package form	GRID ARRAY
power supply	0.75/1.35 V
Certification status	Not Qualified
speed	1200 MHz
Maximum slew rate	48000 mA
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal location	BOTTOM
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Intel® Core™ i7-600, i5-500, i5-400

and i3-300 Mobile Processor Series

Datasheet — Volume Two

This is volume 2 of 2. Refer to Document Number 322812 for Volume 1

November 2010

Document Number: 322813-002

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,

BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS

PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,

AND INTL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING

LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY

PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or

life sustaining applications.

Legal Lines and Disclaimers

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel

reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future

changes to them.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device

drivers and applications enabled for Intel® 64 architecture. Processors will not operate (including 32-bit operation) without an

Intel® 64 architecture-enabled BIOS. Performance will vary depending on your hardware and software configurations. Consult with

your system vendor for more information

Intel® Core™ i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series may contain design defects or errors known as errata

which may cause the product to deviate from published specifications. Current characterized errata are available on request.



Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor

family, not across different processor families. See

http://www.intel.com/products/processor_number

for details.

Intel, Intel SpeedStep, Itanium and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

*Other names and brands may be claimed as the property of others.

Datasheet

Contents

Processor Configuration Registers

........................................................................... 12

1.1

1.2

System Address Map.......................................................................................... 14

1.2.1 Legacy Address Range ............................................................................ 17

1.2.2 Main Memory Address Range (1 MB - TOLUD) ............................................ 19

1.2.3 Main Memory Address Space (4 GB to TOUUD) ........................................... 27

1.2.4 PCI Express* Configuration Address Space ................................................ 34

1.2.5 PCI Express Graphics Attach (PEG) ........................................................... 34

1.2.6 Graphics Memory Address Ranges ............................................................ 35

1.2.7 System Management Mode (SMM) ............................................................ 36

1.2.8 SMM and VGA Access through GTT TLB .................................................... 37

1.2.9 I/O Address Space.................................................................................. 37

Configuration Process and Registers..................................................................... 39

1.3.1 Platform Configuration Structure .............................................................. 39

Configuration Mechanisms .................................................................................. 40

1.4.1 Standard PCI Configuration Mechanism ..................................................... 40

1.4.2 PCI Express Enhanced Configuration Mechanism......................................... 40

Routing Configuration Accesses ........................................................................... 42

1.5.1 Internal Device Configuration Accesses...................................................... 43

1.5.2 Bridge Related Configuration Accesses ...................................................... 44

Processor Register Introduction ........................................................................... 45

I/O Mapped Registers ........................................................................................ 46

PCI Device 0 ..................................................................................................... 46

1.8.1 VID - Vendor Identification ...................................................................... 48

1.8.2 DID - Device Identification....................................................................... 48

1.8.3 PCICMD - PCI Command ......................................................................... 49

1.8.4 PCISTS - PCI Status ............................................................................... 51

1.8.5 RID - Revision Identification .................................................................... 52

1.8.6 CC - Class Code ..................................................................................... 53

1.8.7 MLT - Master Latency Timer ..................................................................... 54

1.8.8 HDR - Header Type................................................................................. 54

1.8.9 SVID - Subsystem Vendor Identification .................................................... 54

1.8.10 SID - Subsystem Identification ................................................................. 55

1.8.11 CAPPTR - Capabilities Pointer ................................................................... 55

1.8.12 PXPEPBAR - PCI Express Egress Port Base Address ..................................... 56

1.8.13 MCHBAR - Processor Memory Mapped Register Range Base.......................... 57

1.8.14 GGC - Processor Graphics Control Register................................................. 58

1.8.15 DEVEN - Device Enable ........................................................................... 62

1.8.16 DMIBAR - Root Complex Register Range Base Address ................................ 63

1.8.17 LAC - Legacy Access Control .................................................................... 64

1.8.18 REMAPBASE - Remap Base Address Register .............................................. 66

1.8.19 REMAPLIMIT - Remap Limit Address Register ............................................. 66

1.8.20 TOM - Top of Memory ............................................................................. 67

1.8.21 TOUUD - Top of Upper Usable DRAM ......................................................... 68

1.8.22 GBSM - Graphics Base of Stolen Memory ................................................... 69

1.8.23 BGSM - Base of GTT Stolen Memory.......................................................... 70

1.8.24 TSEGMB - TSEG Memory Base.................................................................. 71

1.8.25 TOLUD - Top of Low Usable DRAM ............................................................ 71

1.3

1.4

1.5

1.6

1.7

1.8

Datasheet

1.9

1.10

1.8.26

1.8.27

1.8.28

1.8.29

1.8.30

1.8.31

1.8.32

1.8.33

Device

1.9.1

1.9.2

1.9.3

1.9.4

1.9.5

1.9.6

1.9.7

1.9.8

1.9.9

1.9.10

1.9.11

1.9.12

1.9.13

1.9.14

1.9.15

1.9.16

1.9.17

1.9.18

1.9.19

1.9.20

1.9.21

1.9.22

1.9.23

1.9.24

1.9.25

1.9.26

1.9.27

1.9.28

1.9.29

1.9.30

1.9.31

1.9.32

1.9.33

1.9.34

1.9.35

1.9.36

Device

1.10.1

1.10.2

1.10.3

1.10.4

1.10.5

1.10.6

1.10.7

PBFC - Primary Buffer Flush Control ..........................................................73

SBFC - Secondary Buffer Flush Control ......................................................73

ERRSTS - Error Status .............................................................................74

ERRCMD - Error Command.......................................................................75

SMICMD - SMI Command.........................................................................76

SCICMD - SCI Command .........................................................................77

SKPD - Scratchpad Data ..........................................................................77

CAPID0 - Capability Identifier ...................................................................78

0 MCHBAR DRAM Controls ........................................................................78

CSZMAP - Channel Size Mapping...............................................................80

CHDECMISC - Channel Decode Misc. .........................................................81

C0DRB0 - Channel 0 DRAM Rank Boundary Address 0 .................................83

C0DRB1 - Channel 0 DRAM Rank Boundary Address 1 .................................84

C0DRB2 - Channel 0 DRAM Rank Boundary Address 2 .................................84

C0DRB3 - Channel 0 DRAM Rank Boundary Address 3 .................................85

C0DRA01 - Channel 0 DRAM Rank 0,1 Attribute ..........................................85

C0DRA23 - Channel 0 DRAM Rank 2,3 Attribute ..........................................87

C0CYCTRKPCHG - Channel 0 CYCTRK PCHG ...............................................88

C0CYCTRKACT - Channel 0 CYCTRK ACT ....................................................89

C0CYCTRKWR - Channel 0 CYCTRK WR......................................................90

C0CYCTRKRD - Channel 0 CYCTRK READ ...................................................91

C0CYCTRKREFR - Channel 0 CYCTRK REFR.................................................92

C0REFRCTRL - Channel 0 DRAM Refresh Control .........................................92

C0CKECTRL - Channel 0 CKE Control .........................................................95

C0ODTCTRL - Channel 0 ODT Control ........................................................96

C0DTC - Channel 0 DRAM Throttling Control...............................................97

C0DTPEW - Channel 0 DRAM Rank Throttling Passive Event..........................98

C0DTAEW - Channel 0 DRAM Rank Throttling Active Event ...........................99

C1DRB0 - Channel 1 DRAM Rank Boundary Address 0 .................................99

C1DRB1 - Channel 1 DRAM Rank Boundary Address 1 ............................... 100

C1DRB2 - Channel 1 DRAM Rank Boundary Address 2 ............................... 100

C1DRB3 - Channel 1 DRAM Rank Boundary Address 3 ............................... 101

C1DRA01 - Channel 1 DRAM Rank 0,1 Attributes....................................... 101

C1DRA23 - Channel 1 DRAM Rank 2,3 Attributes....................................... 102

C1CYCTRKPCHG - Channel 1 CYCTRK PCHG ............................................. 102

C1CYCTRKACT - Channel 1 CYCTRK ACT .................................................. 103

C1CYCTRKWR - Channel 1 CYCTRK WR.................................................... 104

C1CYCTRKRD - Channel 1 CYCTRK READ ................................................. 105

C1CKECTRL - Channel 1 CKE Control ....................................................... 106

C1REFRCTRL - Channel 1 DRAM Refresh Control ....................................... 107

C1ODTCTRL - Channel 1 ODT Control ...................................................... 110

C1DTC - Channel 1 DRAM Throttling Control............................................. 111

C1DTPEW - Channel 1 DRAM Rank Throttling Passive Event........................ 112

C1DTAEW - Channel 1 DRAM Rank Throttling Active Event ......................... 113

DDRMPLL1 - DDR PLL BIOS .................................................................... 114

0 MCHBAR Thermal Management Controls ................................................ 114

TSC1 - Thermal Sensor Control 1 ............................................................ 116

TSS1 - Thermal Sensor Status 1 ............................................................. 117

TR1 - Thermometer Read 1 .................................................................... 118

TOF1 - Thermometer Offset 1................................................................. 119

RTR1 - Relative Thermometer Read 1 ...................................................... 119

TSTTPA1 - Thermal Sensor Temperature Trip Point A1 ............................... 120

TSTTPB1 - Thermal Sensor Temperature Trip Point B1 ............................... 121

Datasheet

1.11

1.12

1.13

1.10.8 HWTHROTCTRL1 - Hardware Throttle Control 1 ........................................ 122

1.10.9 TIS1 - Thermal Interrupt Status 1 .......................................................... 123

1.10.10TERATE - Thermometer Mode Enable and Rate ......................................... 125

1.10.11TERRCMD - Thermal Error Command ...................................................... 127

1.10.12TSMICMD - Thermal SMI Command ........................................................ 128

1.10.13TSCICMD - Thermal SCI Command ......................................................... 129

1.10.14TINTRCMD - Thermal INTR Command ..................................................... 130

1.10.15EXTTSCS - External Thermal Sensor Control and Status............................. 131

1.10.16MCHTSWDT - Memory Controller Thermal Sensor Watch Dog Timer ............ 133

1.10.17MEMTDPCTW - Memory TDP Controller Registers ...................................... 133

1.10.18MTDPCCRWTWHOTTH - Memory TDP Controller Combined RD/WR Thermal

Weight Hot Thresholds .......................................................................... 134

1.10.19MTDPCCRWTWHOTTH2 - Memory TDP Controller Combined RD/WR Thermal

Weight Hot Thresholds 2 ....................................................................... 136

1.10.20MTDPCCRWTWHOTTH3 - Memory TDP Controller Combined RD/WR Thermal

Weight Hot Thresholds 3 ....................................................................... 137

1.10.21MTDPCCRWTWHOTTH4 - Memory TDP Controller Combined RD/WR Thermal

Weight Hot Thresholds 4 ....................................................................... 138

1.10.22MTDPCHOTTHINT - Memory TDP Controller Hot Throttled Intervals ............. 139

1.10.23MTDPCHOTTHINT2 - Memory TDP Controller Hot Throttled Intervals 2 ......... 140

1.10.24MTDPCTLAUXTNTINT - Memory TDP Controller Aux and Throttle-NonThrottle

Intervals ............................................................................................. 141

1.10.25MTDPCMISC - Memory TDP Controller Miscellaneous Control ...................... 141

1.10.26TSFUSE - Thermal Sensor Fuses ............................................................. 142

MCHBAR Render Thermal Throttling Controls....................................................... 143

1.11.1 THERMSTCTL – Render Thermal State Control .......................................... 143

1.11.2 RSTDBYCTL - Render Standby State Control ............................................ 144

1.11.3 VIDCTL - VID Control ............................................................................ 145

1.11.4 WDTMRTS - Watchdog Timer For Thermal Sensor Trip ............................... 145

1.11.5 WDTSTPSZ - Watchdog Timer Based Px Step Size..................................... 145

Device 0 MCHBAR ACPI Power Management Controls ........................................... 146

1.12.1 C3C6ET - C3/C6 EntryTimers ................................................................. 146

1.12.2 SLFRCS - Self-Refresh Channel Status..................................................... 147

1.12.3 DSLFRC - PM Memory Subsystem ........................................................... 147

1.12.4 PMCFG - Power Management Configuration ............................................. 148

PCI Device1.................................................................................................... 148

1.13.1 VID1 - Vendor Identification .................................................................. 151

1.13.2 DID1 - Device Identification ................................................................... 151

1.13.3 PCICMD1 - PCI Command...................................................................... 152

1.13.4 PCISTS1 - PCI Status............................................................................ 154

1.13.5 RID1 - Revision Identification................................................................. 156

1.13.6 CC1 - Class Code.................................................................................. 157

1.13.7 CL1 - Cache Line Size ........................................................................... 157

1.13.8 HDR1 - Header Type ............................................................................. 158

1.13.9 PBUSN1 - Primary Bus Number .............................................................. 158

1.13.10SBUSN1 - Secondary Bus Number .......................................................... 159

1.13.11SUBUSN1 - Subordinate Bus Number ...................................................... 159

1.13.12IOBASE1 - I/O Base Address.................................................................. 160

1.13.13IOLIMIT1 - I/O Limit Address ................................................................. 160

1.13.14SSTS1 - Secondary Status ..................................................................... 161

1.13.15MBASE1 - Memory Base Address ............................................................ 162

1.13.16MLIMIT1 - Memory Limit Address............................................................ 162

1.13.17PMBASE1 - Prefetchable Memory Base Address ........................................ 163

Datasheet

CN80617006042AB/SLBUG Related Products

	CN80617006042AB/SLBUG	CP80617004116AD/SLBPG	CN80617004116AD/SLBPF	R35I-200/4-8MM-LD/PP-5/0-7-A-C	CN80617005352AA/SLBQP	CP80617005487AD/SLC28	CP80617003981AH/SLBPD	CP80617004116AH/SLBZX
Description	RISC Microprocessor, 64-Bit, 1200MHz, CMOS, PBGA1288	RISC Microprocessor, 64-Bit, 2530MHz, CMOS, PPGA988	RISC Microprocessor, 64-Bit, 2530MHz, CMOS, PBGA1288	Rotary Position Encoder, Single,	RISC Microprocessor, 64-Bit, 1060MHz, CMOS, PBGA1288	RISC Microprocessor, 64-Bit, 2660MHz, CMOS, PPGA988	RISC Microprocessor, 64-Bit, 2660MHz, CMOS, PPGA988	RISC Microprocessor, 64-Bit, 2530MHz, CMOS, PPGA988
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Reach Compliance Code	compliant	compli	compli	unknown	compliant	unknown	compliant	compliant
surface mount	YES	NO	YES	NO	YES	NO	NO	NO
bit size	64	64	64	-	64	64	64	64
Number of terminals	1288	988	1288	-	1288	988	988	988
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	PGA	BGA	-	BGA	PGA	PGA	PGA
Encapsulate equivalent code	BGA1288(UNSPEC)	PGA988,35X36,40	BGA1288(UNSPEC)	-	BGA1288(UNSPEC)	PGA988,35X36,40	PGA988,35X36,40	PGA988,35X36,40
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	-	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
power supply	0.75/1.35 V	0.75/1.35 V	0.75/1.35 V	-	0.75/1.35 V	0.75/1.35 V	0.75/1.35 V	0.75/1.35 V
Certification status	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
speed	1200 MHz	2530 MHz	2530 MHz	-	1060 MHz	2660 MHz	2660 MHz	2530 MHz
Maximum slew rate	48000 mA	48000 mA	48000 mA	-	48000 mA	48000 mA	48000 mA	48000 mA
technology	CMOS	CMOS	CMOS	-	CMOS	CMOS	CMOS	CMOS
Terminal form	BALL	PIN/PEG	BALL	-	BALL	PIN/PEG	PIN/PEG	PIN/PEG
Terminal location	BOTTOM	PERPENDICULAR	BOTTOM	-	BOTTOM	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	-	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC
Base Number Matches	-	1	1	-	1	1	1	-

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