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Chapter Revision Dates
Chapter 1. Cyclone III Device Family Overview
Revised:
May 2008
Part number:
CIII51001-1.2
Chapter 2. Logic Elements and Logic Array Blocks in Cyclone III Devices
Revised:
July 2007
Part number:
CIII51002-1.1
Chapter 3. MultiTrack Interconnect in Cyclone III Devices
Revised:
May 2008
Part number:
CIII51003-1.2
Chapter 4. Memory Blocks in Cyclone III Devices
Revised:
May 2008
Part number:
CIII51004-1.2
Chapter 5. Embedded Multipliers in Cyclone III Devices
Revised:
July 2007
Part number:
CIII51005-1.1
Chapter 6. Clock Networks and PLLs in Cyclone III Devices
Revised:
May 2008
Part number:
CIII51006-2.0
Chapter 7. Cyclone III Device I/O Features
Revised:
May 2008
Part number:
CIII51007-2.0
Chapter 8. High-Speed Differential Interfaces in Cyclone III Devices
Revised:
May 2008
Part number:
CIII51008-1.2
Chapter 9. External Memory Interfaces in Cyclone III Devices
Revised:
May 2008
Part number:
CIII51009-1.2
Chapter 10. Configuring Cyclone III Devices
Revised:
May 2008
Part number:
CIII51010-2.0
Chapter 11. Hot Socketing and Power-On Reset in Cyclone III Devices
Revised:
July 2007
Part number:
CIII51011-1.1
Chapter 12. Remote System Upgrade With Cyclone III Devices
Revised:
July 2007
Part number:
CIII51012-1.1
Chapter 13. SEU Mitigation in Cyclone III Devices
Revised:
May 2008
Part number:
CIII51013-1.2
Chapter 14. IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone III Devices
Revised:
May 2008
Part number:
CIII51014-1.2
Altera Corporation
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Contents
Chapter Revision Dates ........................................................................................................ iii
About this Handbook .......................................................................................................... xiii
How to Contact Altera .......................................................................................................................................................................... xiii
Typographic Conventions .................................................................................................................................................................... xiii
Section 1. Device Core
Chapter 1. Cyclone III Device Family Overview
Cyclone III: Lowest System-Cost FPGAs .......................................................................................................................................... 1–1
Cyclone III Device Features ................................................................................................................................................................ 1–1
Reduced Cost ................................................................................................................................................................................... 1–1
Lowest-Power 65-nm FPGA .......................................................................................................................................................... 1–1
Increased System Integration ........................................................................................................................................................ 1–1
Cyclone III Device Architecture ......................................................................................................................................................... 1–4
LEs and LABs ................................................................................................................................................................................... 1–5
MultiTrack Interconnect ................................................................................................................................................................. 1–5
Memory Blocks ................................................................................................................................................................................ 1–6
Embedded Multipliers and Digital Signal Processing Support ............................................................................................... 1–6
I/O Features ..................................................................................................................................................................................... 1–7
Clock Networks and PLLs ............................................................................................................................................................. 1–7
High-Speed Differential Interfaces ............................................................................................................................................... 1–8
Auto-Calibrating External Memory Interfaces ........................................................................................................................... 1–8
Quartus II Software Support ......................................................................................................................................................... 1–8
Nios II—the World’s Most Versatile Embedded Processor ...................................................................................................... 1–8
Configuration ................................................................................................................................................................................... 1–9
Remote System Upgrades .............................................................................................................................................................. 1–9
Hot Socketing and Power-On-Reset ............................................................................................................................................. 1–9
SEU Mitigation ................................................................................................................................................................................. 1–9
JTAG Boundary Scan Testing ........................................................................................................................................................ 1–9
Reference and Ordering Information .............................................................................................................................................. 1–10
Referenced Documents ...................................................................................................................................................................... 1–10
Document Revision History .............................................................................................................................................................. 1–11
Chapter 2. Logic Elements and Logic Array Blocks in Cyclone III Devices
Introduction ...........................................................................................................................................................................................
Overview ................................................................................................................................................................................................
Logic Elements ......................................................................................................................................................................................
LE Features .......................................................................................................................................................................................
LE Operating Modes ............................................................................................................................................................................
Logic Array Blocks ...............................................................................................................................................................................
Topology ...........................................................................................................................................................................................
LAB Interconnects ...........................................................................................................................................................................
LAB Control Signals .............................................................................................................................................................................
Conclusion .............................................................................................................................................................................................
Document Revision History ................................................................................................................................................................
2–1
2–1
2–1
2–2
2–4
2–6
2–6
2–7
2–7
2–8
2–8
Chapter 3. MultiTrack Interconnect in Cyclone III Devices
Introduction ........................................................................................................................................................................................... 3–1
MultiTrack Interconnect ...................................................................................................................................................................... 3–1
Row Interconnects ........................................................................................................................................................................... 3–1
Altera Corporation
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