C1632C681M3RAC datasheet, PDF - EEWORLD Datasheet

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C1632C681M3RAC: DescriptionISOLATED C NETWORK, 25V, X7R, 0.00068uF, SURFACE MOUNT, CHIP-8, CHIP, ROHS COMPLIANT; CategoryPassive components capacitor; File Size777KB，2 Pages; ManufacturerKEMET; Websitehttp://www.kemet.com; Environmental Compliance

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C1632C681M3RAC Overview

ISOLATED C NETWORK, 25V, X7R, 0.00068uF, SURFACE MOUNT, CHIP-8, CHIP, ROHS COMPLIANT

C1632C681M3RAC Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	KEMET
package instruction	CHIP,
Reach Compliance Code	compliant
ECCN code	EAR99
capacitance	0.00068 µF
Capacitor type	ARRAY/NETWORK CAPACITOR
JESD-609 code	e3
length	3.2 mm
Manufacturer's serial number	C
Installation features	SURFACE MOUNT
negative tolerance	20%
Network Type	ISOLATED C NETWORK
Number of components	1
Number of functions	4
Number of terminals	8
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
encapsulated code	CHIP
Package shape	RECTANGULAR PACKAGE
positive tolerance	20%
Rated (DC) voltage (URdc)	25 V
Maximum seat height	1.35 mm
surface mount	YES
Temperature characteristic code	X7R
Temperature Coefficient	15% ppm/°C
Terminal surface	Tin (Sn) - with Nickel (Ni) barrier
Terminal pitch	0.8 mm
Terminal shape	WRAPAROUND
width	1.6 mm

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CERAMIC CAPACITOR ARRAY

FEATURES

•

Four individual capacitors inside

one 1206 monolithic structure

Saves board and inventory space

One placement instead of four - less costly

•

Easier to handle and solder than 4 smaller chips

Tape and reel per EIA 481-1

RoHS Compliant

CAPACITOR OUTLINE DRAWING

P/2

Ref

BW1

TABLE 1

EIA DIMENSIONS – MILLIMETERS (INCHES)

Size

Code

1632

Length

3.2 (0.126)

0.2 (0.008)

Width

1.6 (.063)

0.2 (.008)

Thickness

T (max.)

0.7 - 1.35

(0.027 - 0.053)

Bandwidth

BW1

Pitch

0.40 (0.016)

0.1 - 0.5

0.8 (0.031)

0.2 (0.008) (0.004 - 0.020)

0.1 (0.004)

Notes:

1. Metric is controlling - English for reference only.

2. Pitch (P) tolerances are non-cumulative along the package.

3. Thickness (T) depends on capacitance.

CERAMIC ARRAY ORDERING INFORMATION

1632

103

END METALLIZATION

C-Standard

(Tin-plated nickel barrier)

FAILURE RATE LEVEL

A- Not Applicable

TEMPERATURE CHARACTERISTIC

Designated by Capacitance

Change Over T

emperature Range

G – C0G (NP0) (±30 PPM/°C)

R – X7R (±15%)

VOLTAGE

5 = 50v; 3 = 25v; 4 = 16v; 8=10v

CERAMIC

EIA SIZE CODE

Ceramic chip array

SPECIFICATION

C - Standard

CAPACITANCE CODE

Expressed in Picofarads (pF)

First two digits represent significant figures.

Third digit specifies number of zeros. (Use 9

for 1.0 thru 9.9pF (Example: 2.2pF = 229

CAPACITANCE TOLERANCE

K –

±10%:

M –

±20%

Standard Tolerances

Contact factory for any special requirements.

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Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

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