1N4754A

By: Edwin Robledo, General Manager, CadSoft USA Despite the increasing integration of semiconductors, the availability of readily available systems-on-chip for many applications, and the inc...[Details]

On September 12, it was reported that due to the rapid development of companies such as NVIDIA in the field of AI chips, TSMC's demand for advanced packaging services has surged, and it has been fo...[Details]

Abstract: Using VHDL language and graphic input design method, this paper gives the specific method of using CPLD to realize address decoding, serial port expansion, module testing, analog-to-digital ...[Details]

Abstract: T=0 is a contact CPU card communication protocol specified in the international standard. Combined with development practice, the protocol is divided into four levels. Starting from the pers...[Details]

Abstract: This paper introduces the principle of block DMA high-speed data acquisition circuit and its CPLD implementation. Using CPLD to design dual-port RAM cache, control decoding, and sequential l...[Details]

On October 23, ChipLink Integrated, a leading one-stop chip system foundry in China, reached a comprehensive strategic cooperation agreement with Yuxin Electronic Technology Group, a key enterpri...[Details]

For a long time, the application of comparators has been impacted by operational amplifiers. Until now, with the continuous improvement of comparator performance indicators, this situation has been...[Details]

The PLL1700 is an inexpensive, multi-clock generator phase-locked loop (PLL). It generates four system clocks from a 27MHz reference input frequency. It allows users to reduce cost and save space b...[Details]

Abstract: AD605 is a low-noise, dual-channel, dB linear variable gain amplifier produced by AD. It can be used for ultrasonic and time gain control, high-performance AGC system and signa...[Details]

Abstract: This paper introduces the principle and implementation method of using modern EDA to design a common instrument for nuclear physics experiments, the calibrator. The new calibrator uses FPGA ...[Details]

Abstract: Combining Petri net with VHDL, using Petri net to build a hardware system model, then using VHDL language to design, and finally downloading to CPLD, successfully realized the logic controll...[Details]

Abstract: This paper introduces the interface design of the read and write logic function module between the single-chip microcomputer and the Xilinx XC9500 series programmable logic device, as well a...[Details]

The relationship between the size of the electroplating tank and the average loading capacity, cathode current density, volume current density, etc.; Generally speaking, the size of the electroplating...[Details]

Although the current EDA tools are very powerful, as the PCB size requirements are getting smaller and smaller and the device density is getting higher and higher, the difficulty of PCB design is not ...[Details]

Abstract: This paper introduces the hardware structure and working principle of the high-speed image acquisition system, describes the VHDL module design of FPGA in the image acquisition and data stor...[Details]