555 power-on delay output high level circuit

Introduction to circuit principle The circuit is shown in Figure 3-1. When the power
is turned on, capacitor c1 has no time to charge. The ② and ⑥ pins of 555
are at high level, and the ③ pin outputs low level. As the capacitor Cl charges
, the potential of pins ② and ⑥ of 555 begins to decrease. When the potential of pin ② is lower than
Vcc, the circuit flips, and the output terminal U{. changes from low level to high level
, and remains so. c boot delay time·Av hand 1. IRC. The diode VD is set up to discharge the capacitor
C after the power is turned off . This circuit is generally used to control the delayed turn-on of the power circuit.     (2) Component parameter selection The selection of components is shown in Figure 3-1, subject to special requirements.     (3) The 555 power-on delay output high-level circuit is shown in Figure 3-1.