DS3013 - 2.2
ZN448/ZN449
8-BIT MICROPROCESSOR COMPATIBLE A-D CONVERTER
The ZN448 and ZN449 are 8-bit successive
approximation A-D converters designed to be easily
interfaced to microprocessors. All active circuitry is contained
on-chip including a clock generator and stable 2.5V bandgap
reference, control logic and double buffered latches with
reference.
Only a reference resistor and capacitor, clock resistor and
capacitor and input resistors are required for operation with
either unipolar or bipolar input voltage.
BUSY (END OF CONVERSION)
RD (OUTPUT ENABLE)
CLOCK
WR (START CONVERSION)
R
EXT
V
IN
V
REF
IN
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
DB
0
(LSB)
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
(MSB)
+V
CC
(+5V)
FEATURES
s
s
s
s
s
s
s
Easy Interfacing to Microprocessor, or operates as a
'Stand-Alone' Converter
Fast: 9 microseconds Conversion time Guaranteed
Choice of Linearity: 0.5 LSB - ZN448, 1 LSB - ZN449
On-Chip Clock
Choice of On-Chip or External Reference Voltage
Unipolar or Bipolar Input Ranges
Commercial Temperature Range
V
REF
OUT
GROUND
ZN448/9E (DP18)
BUSY (END OF CONVERSION)
RD (OUTPUT ENABLE)
CLOCK
WR (START CONVERSION)
R
EXT
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
DB
0
(LSB)
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
(MSB)
+V
CC
(+5V)
ORDERING INFORMATION
Device type
ZN448E
ZN449D
ZN449E
Linearity
error (LSB)
0.5
1
1
Operating
temperature
0°C to +70°C
0°C to +70°C
0°C to +70°C
Package
DP18
MP18
DP18
V
IN
V
REF
IN
V
REF
OUT
GROUND
ZN449D (MP18)
Fig.1 Pin connection - top view
COMPARATOR
ANALOGUE
INPUT
VREF IN
6
+
5
REXT
7
8-BIT DAC
-
VREF OUT
8
2.5V
REFERENCE
CLOCK
GENERATOR
3
CK RC OR
EXT CLOCK
GROUND
9
SUCCESSIVE
APPROXIMATION REGISTER
INTERFACE
AND
CONTROL
LOGIC
4
WR
1
BUSY
VCC (+5V)
10
3-STATE BUFFERS
2
RD
11
DB7
12
13
14
15
16
17
18
DB0
Fig.2 System diagram
ZN448/9
ABSOLUTE MAXIMUM RATINGS
Supply voltage V
CC
Max. voltage, logic and V
REF
input
Operating temperature range
Storage temperature range
+7
+V
CC
0°C to +70°C (MP and DP package)
-55°C to +125°C
ELECTRICAL CHARACTERISTICS
(at V
CC
= 5V, T
amb
= 25°C and f
CLK
= 1.6MHz unless otherwise specified).
Parameter
ZN448
Linearity error
Differential linearity error
Zero transition
(00000000→00000001)
Full-scale→transition
(11111110 11111111)
ZN449
Linearity error
Differential linearity error
Zero transition
(00000000→00000001)
Full-scale→transition
(11111110 11111111)
All Types
Resolution
Linearity temperature coefficient
Differential linearity temperature coefficient
Full-scale temperature coefficient
Zero temperature coefficient
Reference input range
Supply voltage
Supply current
Power consumption
Comparator
Input current
Input resistance
Tail current
Negative supply
Input voltage
On-chip reference
Output voltage
ZN448
ZN449
Slope resistance
V
REF
temperature coefficient
Reference current
Min.
Typ.
Max.
±0.5
±0.75
18
2.555
Units
LSB
LSB
mV
V
Conditions
-
-
12
2.545
-
-
15
2.550
DP package
V
REF
= 2.560V
-
-
7
10
2.542
-
-
12
15
2.550
±1
±1
17
20
2.558
LSB
LSB
mV
mV
V
MP package
DP package
V
REF
= 2.560V
8
-
-
-
-
1
4.5
-
-
-
±3
±6
±2.5
±8
-
5
25
125
-
-
-
-
-
3
5.5
40
200
bits
ppm/°C
ppm/°C
ppm/°C
µV/°C
V
V
mA
mW
µA
kΩ
µA
V
V
-
-
25
-3
-0.5
1
100
65
-5
-
-
-
150
-30
+3.5
V
IN
= +3V, R
EXT
= 82kΩ
V - = -5V
2.520
2.520
-
-
4
2.550
2.550
0.5
50
-
2.580
2.600
2
-
15
V
Ω
ppm/°C
mA
R
REF
= 390Ω
C
REF
= 4µ7
2
ZN448/9
ELECTRICAL CHARACTERISTICS
(Cont.)
Parameter
Clock
On-chip clock frequency
Clock frequency temperature coefficient
Clock resistor
Maximum external clock frequency
Clock pulse width
High level input voltage V
IH
Low level input voltage V
IL
High level input current I
IH
Low level input current I
IL
Logic
(over operating temperature range)
Convert input
High level input voltage V
IH
Low level input voltage V
IL
High level input current I
IH
Low level input current I
IL
RD
input
High level input voltage V
IH
Low level input voltage V
IL
High level input current I
IH
Low level input current I
IL
High level output voltage V
OH
Low level output voltage V
OL
High level output current I
OH
Low level output current I
OL
Three-state disable output leakage
Input clamp diode voltage
RD
input to data output
Enable/disable delay times T
E1
T
E0
T
D1
T
D0
Convert pulse width t
WR
WR
input to
BUSY
output
Min.
Typ.
Max.
Units
MHz
%/°C
kΩ
MHz
ns
V
V
µA
µA
Conditions
-
-
-
0.9
500
4
-
-
-
-
+0.5
-
-
-
-
-
-
-
1
-
2
1
-
-
0.8
800
-500
V
IN
= +4V, V
CC
= MAX
V
IN
= +0.8V, V
CC
= MAX
2
-
-
-
-
-
300
±10
-
0.8
-
-
V
V
µA
µA
V
IN
= +2.4V, V
CC
= MAX
V
IN
= +0.4V, V
CC
= MAX
2
-
-
-
2.4
-
-
-
-
-
-
180
60
80
60
200
-
-
-
+150
-300
-
-
-
-
-
-
180
210
80
110
80
-
-
-
0.8
-
-
-
0.4
-100
1.6
2
-1.5
250
260
100
140
100
-
250
V
V
µA
µA
V
V
µA
mA
µA
V
ns
ns
ns
ns
ns
ns
ns
V
IN
= +2.4V, V
CC
= MAX
V
IN
= +0.4V, V
CC
= MAX
I
OH
= +2.4V, V
CC
= MAX
I
OL
= +0.4V, V
CC
= MAX
V
OUT
= +2V
GENERAL CIRCUIT OPERATION
The ZN448/9 utilises the successive approximation
technique. Upon receipt of a negative-going pulse at the
WR
input the
BUSY
output goes low, the MSB is set to 1 and all
other bits are set to 0, which produces an output voltage of
V
REF/2
from the DAC. This is compared to the input voltage V
IN
;
a decision is made on the next negative clock edge to reset the
MSB to 0 if
V
REF
V
REF
< V
IN
or leave it set to 1 if
2
2
< V
IN
.
During a conversion the RD input will normally be held high to
keep the three-state buffers in their high impedance state.
Data can be read out by taking
RD
low, thus enabling the
three-state output. Readout is non-destructive.
CONVERSION TIMING
The ZN448/9 will accept a low-going CONVERT pulse, which
can be completely asynchronous with respect to the clock,
and will produce valid data between 7.5 and 8.5 clock pulses
later depending on the relative timing of the clock and
CONVERT signals. Timing diagrams for the conversion are
shown in Fig.3.
The converter is cleared by a low-going CONVERT pulse,
which sets the most significant bit and results all the other bits
and the
BUSY
flag. Whilst the CONVERT input is low the MSB
output of the DAC is continuously compared with the analogue
input, but otherwise the converter is inhibited.
Bit 2 is set to 1 on the same clock edge, producing an output
V
REF
V
REF
V
REF
from the DAC of
or
+
depending on the state
4
2
4
of the MSB. This voltage is compared to V
IN
and on the next
clock edge a decision is made regarding bit 2, whilst bit 3 is set
to 1. This procedure is repeated for all eight bits. On the eighth
negative clock edge
BUSY
goes high indicating that the
conversion is complete.
3
ZN448/9
After the CONVERT input goes high again the MSB decision
is made and the successive approximation routine runs to
completion.
The CONVERT pulse can be as short as 200ns; however the
MSB must be allowed to settle for at least 550ns before the
MSB decision is made. To ensure that this criterion is met
even with short CONVERT pulses the converter waits, after
the CONVERT input goes high, for a rising clock edge followed
by a falling clock edge, the MSB decision being taken on the
falling clock edge. This ensures that the MSB is allowed to
settle for at least half a clock period, or 550ns at maximum
clock frequency. The CONVERT input is not locked out during
a conversion and if it is oulsed low at any time the converter
will restart.
The
BUSY
output goes high simultaneously with the LSB
decision, at the end of a conversion indicating data valid. Note
that if the three-state data outputs are enabled during a
conversion the valid data will be available at the outputs after
the rising edge of the
BUSY
signal. If, however the outputs are
not enabled until after
BUSY
goes high then the data will be
subject to the propagation delay of the three-state buffers.
(See under DATA OUTPUTS).
Fig.3 ZN448/9 timing diagram
4
ZN448/9
If a free-running conversion is required, then the converter can
be made to cycle by inverting the
BUSY
output and feeding it
to
WR.
To ensure that the converter starts reliably after power-
up an initial start pulse is required. This can be ensured by
using a NOR gate instead of an inverter and feeding it with a
positive-going pulse which can be derived from a simple RC
network that gives a single pulse when power is applied, as
shown in Fig.4a.
The ADC will complete a conversion on every eighth clock
pulse, with the
BUSY
output going high for a period
determined by the propagation delay of the NOR gate, during
which time the data can be stored in a latch. The time available
for storing data can be increased by inserting delays into the
inverter path.
A timing diagram for the continuous conversion mode is
shown in Fig.3b.
As the
BUSY
output uses a passive pull-up the rise time of this
output depends on the RC time constant of the pull-up resistor
and load capacitance. In the continuous conversion mode the
use of a 4k7 external pull-up resistor is recommended to
reduce the risetime and ensure that a logic 1 level is reached.
Fig.4a Circuit for continuous conversion
Fig.4b Timing for continuous conversion
DATA OUTPUTS
The data outputs are provided with three-state buffers to allow
connection to a common data bus. An equivalent circuit is
shown in Fig.5. Whilst the
RD
input is high both output
transistors are turned off and the ZN448/9 presents only a high
impedance load to the bus.
When
RD
is low the data outputs will assume the logic states
present at the outputs of the successive register.
A test circuit and timing diagram for the output enable/disable
delays are given in Fig.6.
5
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