Preliminary
‡
512Mb: x32 Automotive Mobile LPDDR2 SDRAM
Features
Automotive Mobile LPDDR2 SDRAM
EDB5432BEBH, EDB5432BEPA
Features
• Ultra low-voltage core and I/O power supplies
– V
DD2
= 1.14–1.30V
– V
DDCA
/V
DDQ
= 1.14–1.30V
– V
DD1
= 1.70–1.95V
• Clock frequency range
– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)
• Four-bit prefetch DDR architecture
• Four internal banks for concurrent operation
1
• Multiplexed, double data rate, command/address
inputs; commands entered on every CK edge
• Bidirectional/differential data strobe per byte of
data (DQS/DQS#)
• Programmable READ and WRITE latencies (RL/WL)
• Programmable burst lengths: 4, 8, or 16
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock stop capability
• RoHS-compliant, “green” packaging
Table 1: Key Timing Parameters
Speed Clock Rate Data Rate
Grade
(MHz)
(Mb/s/pin)
-1D
533
1066
RL
8
WL
4
t
RCD/
t
RP
1
Options
• V
DD2
: 1.2V
• Configuration
– 4 Meg x 32 x 4 banks x 1 die
• Device type
– LPDDR2-S4, 1 die in package
• FBGA “green” package
– 134-ball VFBGA
(10mm x 11.5mm)
– 168-ball WFBGA
(12mm x 12mm)
• Timing – cycle time
– 1.875ns @ RL = 8
• Special options
– Standard
– Automotive certified
(Package-level burn-in)
• Operating temperature range
– From –40°C to +85°C
– From –40°C to +105°C
From –40°C to +125°C
• Revision
Note:
Marking
B
16M32
D
BH
PA
-1D
None
A
IT
AT
UT
:E
1. For fast
t
RCD/
t
RP, contact factory.
Note:In
this data sheet, all features, functions, options
or descriptions related to an 8-bank device do not ap-
ply. For example per-bank refresh, which is specific to
an 8-bank device, is not supported.
Typical
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1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2014 Micron Technology, Inc. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
Preliminary
512Mb: x32 Automotive Mobile LPDDR2 SDRAM
Features
Table 2: Single Channel S4 Configuration Addressing
Architecture
Die configuration
Row addressing
Column addressing
Number of die
Die per rank
Ranks per channel
1
Note:
16 Meg x 32
4 Meg x 32 x 4 banks
8K (A[12:0])
512 (A[8:0])
1
1
1
1. A channel is a complete LPDRAM interface, including command/address and data pins.
Figure 1: 512Mb LPDDR2 Part Numbering
E
D
B
54
32
B
E
BH
1D
A
AT :F
Embedded Memory
Type
D = Packaged device
Design Revision
:F = Lead free (RoHS compliant
and Halogen free)
Operating Temperature
Product Family
B = DDR2 Mobile RAM
IT = –40°C to +85°C
AT = –40°C to +105°C
UT = –40°C to +125°C
Density
54 = 512MB/2KB
Special Options
A = Automotive grade
Organization
32 = x32
Speed (package only)
1D = 1066 Mbps
Power Supply and Interface
B = V
DD1
= 1.8V; V
DD2
= V
DDCA
= V
DDQ
= 1.2V;
S4B device; HSUL
Package
BH = 134-ball VFBGA (10mm x 11.5mm)
PA = 168-ball WFBGA (12mm x 12mm)
Revision = E
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at
www.micron.com/decoder.
Table 3: Package Codes and Descriptions
Package
Code
BH
PA
Notes:
Ball Count
134
168
# Ranks
1
1
# Channels
1
1
Size (mm)
10 x 11.5 x 1.0, 0.65 pitch
12 x 12 x 0.8, 0.5 pitch
Die per
Package
SDP
SDP
Solder Ball
Composition
SAC302
SAC302
1. SDP = Single-die package.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2014 Micron Technology, Inc. All rights reserved.
Preliminary
512Mb: x32 Automotive Mobile LPDDR2 SDRAM
Features
Contents
General Description ......................................................................................................................................... 9
General Notes .............................................................................................................................................. 9
I
DD
Specifications ........................................................................................................................................... 10
Package Block Diagrams ................................................................................................................................. 13
Package Dimensions ....................................................................................................................................... 14
Ball Assignments and Descriptions ................................................................................................................. 16
Functional Description ................................................................................................................................... 19
Power-Up ....................................................................................................................................................... 20
Initialization After RESET (Without Voltage Ramp) ...................................................................................... 22
Power-Off ....................................................................................................................................................... 22
Uncontrolled Power-Off .............................................................................................................................. 23
Mode Register Definition ................................................................................................................................ 23
Mode Register Assignments and Definitions ................................................................................................ 23
ACTIVATE Command ..................................................................................................................................... 34
Read and Write Access Modes ......................................................................................................................... 34
Burst READ Command ................................................................................................................................... 34
READs Interrupted by a READ ..................................................................................................................... 41
Burst WRITE Command .................................................................................................................................. 41
WRITEs Interrupted by a WRITE ................................................................................................................. 44
BURST TERMINATE Command ...................................................................................................................... 44
Write Data Mask ............................................................................................................................................. 46
PRECHARGE Command ................................................................................................................................. 47
READ Burst Followed by PRECHARGE ......................................................................................................... 48
WRITE Burst Followed by PRECHARGE ....................................................................................................... 49
Auto Precharge ........................................................................................................................................... 50
READ Burst with Auto Precharge ................................................................................................................. 50
WRITE Burst with Auto Precharge ............................................................................................................... 51
REFRESH Command ...................................................................................................................................... 53
REFRESH Requirements ............................................................................................................................. 59
SELF REFRESH Operation ............................................................................................................................... 61
Partial-Array Self Refresh – Bank Masking .................................................................................................... 62
Partial-Array Self Refresh – Segment Masking .............................................................................................. 63
MODE REGISTER READ ................................................................................................................................. 64
Temperature Sensor ................................................................................................................................... 66
DQ Calibration ........................................................................................................................................... 68
MODE REGISTER WRITE Command ............................................................................................................... 70
MRW RESET Command .............................................................................................................................. 70
MRW ZQ Calibration Commands ................................................................................................................ 71
ZQ External Resistor Value, Tolerance, and Capacitive Loading ..................................................................... 73
Power-Down .................................................................................................................................................. 73
Deep Power-Down ......................................................................................................................................... 80
Input Clock Frequency Changes and Stop Events ............................................................................................. 81
Input Clock Frequency Changes and Clock Stop with CKE LOW ................................................................... 81
Input Clock Frequency Changes and Clock Stop with CKE HIGH .................................................................. 82
NO OPERATION Command ............................................................................................................................ 82
Simplified Bus Interface State Diagram ........................................................................................................ 82
Truth Tables ................................................................................................................................................... 84
Electrical Specifications .................................................................................................................................. 92
Absolute Maximum Ratings ........................................................................................................................ 92
Input/Output Capacitance .......................................................................................................................... 92
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2014 Micron Technology, Inc. All rights reserved.
Preliminary
512Mb: x32 Automotive Mobile LPDDR2 SDRAM
Features
Electrical Specifications – I
DD
Specifications and Conditions ............................................................................ 93
AC and DC Operating Conditions .................................................................................................................... 96
AC and DC Logic Input Measurement Levels for Single-Ended Signals .............................................................. 98
V
REF
Tolerances .......................................................................................................................................... 99
Input Signal .............................................................................................................................................. 100
AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 102
Single-Ended Requirements for Differential Signals .................................................................................... 103
Differential Input Crosspoint Voltage ......................................................................................................... 105
Input Slew Rate ......................................................................................................................................... 106
Output Characteristics and Operating Conditions ........................................................................................... 106
Single-Ended Output Slew Rate .................................................................................................................. 107
Differential Output Slew Rate ..................................................................................................................... 108
HSUL_12 Driver Output Timing Reference Load ......................................................................................... 110
Output Driver Impedance .............................................................................................................................. 110
Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 111
Output Driver Temperature and Voltage Sensitivity ..................................................................................... 112
Output Impedance Characteristics Without ZQ CalibrationI-V Curves Table – TBD ...................................... 112
Clock Specification ........................................................................................................................................ 114
t
CK(abs),
t
CH(abs), and
t
CL(abs) ................................................................................................................ 115
Clock Period Jitter .......................................................................................................................................... 115
Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 115
Cycle Time Derating for Core Timing Parameters ........................................................................................ 116
Clock Cycle Derating for Core Timing Parameters ....................................................................................... 116
Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 116
Clock Jitter Effects on READ Timing Parameters .......................................................................................... 116
Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 117
Refresh Requirements .................................................................................................................................... 118
AC Timing ..................................................................................................................................................... 119
CA and CS# Setup, Hold, and Derating ........................................................................................................... 125
Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 132
Revision History ............................................................................................................................................ 139
Rev. A – 07/15 ............................................................................................................................................ 139
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2014 Micron Technology, Inc. All rights reserved.
Preliminary
512Mb: x32 Automotive Mobile LPDDR2 SDRAM
Features
List of Figures
Figure 1: 512Mb LPDDR2 Part Numbering ....................................................................................................... 2
Figure 2: V
DD1
Typical Self-Refresh Current vs. Temperature – TBD .................................................................. 12
Figure 3: V
DD2
Typical Self-Refresh Current vs. Temperature – TBD .................................................................. 12
Figure 4: Single Rank, Single Channel Package Block Diagram ......................................................................... 13
Figure 5: 134-Ball VFBGA – 10mm x 11.5mm (Package Code: BH) .................................................................... 14
Figure 6: 168-Ball WFBGA – 12mm x 12mm (Package Code: PA) ....................................................................... 15
Figure 7: 134-Ball VFBGA (x32) ...................................................................................................................... 16
Figure 8: 168-Ball WFBGA – 12mm x 12mm .................................................................................................... 17
Figure 9: Functional Block Diagram ............................................................................................................... 19
Figure 10: Voltage Ramp and Initialization Sequence ...................................................................................... 22
Figure 11: ACTIVATE Command .................................................................................................................... 34
Figure 12: READ Output Timing –
t
DQSCK (MAX) ........................................................................................... 35
Figure 13: READ Output Timing –
t
DQSCK (MIN) ........................................................................................... 35
Figure 14: Burst READ – RL = 5, BL = 4,
t
DQSCK >
t
CK ..................................................................................... 36
Figure 15: Burst READ – RL = 3, BL = 8,
t
DQSCK <
t
CK ..................................................................................... 36
Figure 16:
t
DQSCKDL Timing ........................................................................................................................ 37
Figure 17:
t
DQSCKDM Timing ....................................................................................................................... 38
Figure 18:
t
DQSCKDS Timing ......................................................................................................................... 39
Figure 19: Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4 ......................................................... 40
Figure 20: Seamless Burst READ – RL = 3, BL = 4,
t
CCD = 2 .............................................................................. 40
Figure 21: READ Burst Interrupt Example – RL = 3, BL = 8,
t
CCD = 2 ................................................................. 41
Figure 22: Data Input (WRITE) Timing ........................................................................................................... 42
Figure 23: Burst WRITE – WL = 1, BL = 4 ......................................................................................................... 42
Figure 24: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4 ......................................................... 43
Figure 25: Seamless Burst WRITE – WL = 1, BL = 4,
t
CCD = 2 ............................................................................ 43
Figure 26: WRITE Burst Interrupt Timing – WL = 1, BL = 8,
t
CCD = 2 ................................................................ 44
Figure 27: Burst WRITE Truncated by BST – WL = 1, BL = 16 ............................................................................ 45
Figure 28: Burst READ Truncated by BST – RL = 3, BL = 16 ............................................................................... 46
Figure 29: Data Mask Timing ......................................................................................................................... 46
Figure 30: Write Data Mask – Second Data Bit Masked .................................................................................... 47
Figure 31: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(
t
RTP(MIN)/
t
CK) = 2 ................................ 48
Figure 32: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(
t
RTP(MIN)/
t
CK) = 3 ................................ 49
Figure 33: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4 .................................................................. 50
Figure 34: READ Burst with Auto Precharge – RL = 3, BL = 4, RU(
t
RTP(MIN)/
t
CK) = 2 ........................................ 51
Figure 35: WRITE Burst with Auto Precharge – WL = 1, BL = 4 .......................................................................... 52
Figure 36: Regular Distributed Refresh Pattern ............................................................................................... 56
Figure 37: Supported Transition from Repetitive REFRESH Burst .................................................................... 57
Figure 38: Nonsupported Transition from Repetitive REFRESH Burst .............................................................. 58
Figure 39: Recommended Self Refresh Entry and Exit ..................................................................................... 59
Figure 40:
t
SRF Definition .............................................................................................................................. 60
Figure 41: All-Bank REFRESH Operation ........................................................................................................ 61
Figure 42: SELF REFRESH Operation .............................................................................................................. 62
Figure 43: MRR Timing – RL = 3,
t
MRR = 2 ...................................................................................................... 64
Figure 44: READ to MRR Timing – RL = 3,
t
MRR = 2 ......................................................................................... 65
Figure 45: Burst WRITE Followed by MRR – RL = 3, WL = 1, BL = 4 ................................................................... 66
Figure 46: Temperature Sensor Timing ........................................................................................................... 68
Figure 47: MR32 and MR40 DQ Calibration Timing – RL = 3,
t
MRR = 2 ............................................................. 69
Figure 48: MODE REGISTER WRITE Timing – RL = 3,
t
MRW = 5 ....................................................................... 70
Figure 49: ZQ Timings ................................................................................................................................... 72
Figure 50: Power-Down Entry and Exit Timing ................................................................................................ 74
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2014 Micron Technology, Inc. All rights reserved.
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