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EDS2516ADTA-6B-E

Description
Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54,
Categorystorage    storage   
File Size564KB,50 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance
Download Datasheet Parametric View All

EDS2516ADTA-6B-E Overview

Synchronous DRAM, 16MX16, 5.4ns, CMOS, PDSO54,

EDS2516ADTA-6B-E Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMicron Technology
package instructionTSOP, TSOP54,.46,32
Reach Compliance Codecompliant
Maximum access time5.4 ns
Maximum clock frequency (fCLK)166 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PDSO-G54
memory density268435456 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width16
Number of terminals54
word count16777216 words
character code16000000
Maximum operating temperature70 °C
Minimum operating temperature
organize16MX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP
Encapsulate equivalent codeTSOP54,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
power supply3.3 V
Certification statusNot Qualified
refresh cycle8192
Continuous burst length1,2,4,8,FP
Maximum standby current0.002 A
Maximum slew rate0.22 mA
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
PRELIMINARY DATA SHEET
256M bits SDRAM
EDS2516ADTA (16M words
×
16 bits)
Description
The EDS2516ADTA is 256M bits SDRAMs organized
as 4,194,304 words
×
16 bits
×
4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
They are packaged in 54-pin plastic TSOP (II).
Pin Configurations
/xxx indicate active low signal.
54-pin Plastic TSOP (II)
VDD
DQ0
VDDQ
Features
3.3V power supply
Clock frequency: 166MHz/133MHz (max.)
Single pulsed /RAS
×16
organization
4 banks can operate simultaneously and
independently
Burst read/write operation and burst read/single
write operation capability
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
Programmable /CAS latency (CL): 2, 3
Byte control by UDQM and LDQM
Refresh cycles: 8192 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
TSOP (II) package with lead free solder (Sn-Bi)
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
(Top view)
A0 to A12
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
UDQM,LDQM
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
CKE
CLK
VDD
VSS
VDDQ
VSSQ
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
NC
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0544E20 (Ver. 2.0)
Date Published August 2004 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2004
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