EPA1825-10 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> logic> EPA1825-10

EPA1825-10: Description14 Pin DIP High Precision Triple Output TTL Compatible Active Delay Lines; Categorylogic logic; File Size14KB，1 Pages; ManufacturerPCA Electronics Inc.; Websitehttp://www.pca.com/

Download Datasheet Parametric View All

EPA1825-10 Overview

14 Pin DIP High Precision Triple Output TTL Compatible Active Delay Lines

EPA1825-10 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	PCA Electronics Inc.
Parts packaging code	DIP
package instruction	DIP-14/8
Contacts	14/8
Reach Compliance Code	compliant
Other features	MAX RISE TIME CAPTURED
series	TTL
Input frequency maximum value (fmax)	100 MHz
JESD-30 code	R-PDIP-T8
JESD-609 code	e0
Logic integrated circuit type	ACTIVE DELAY LINE
Humidity sensitivity level	3
Number of functions	3
Number of taps/steps	1
Number of terminals	8
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	115 mA
programmable delay line	NO
Prop。Delay @ Nom-Sup	10 ns
Certification status	Not Qualified
Maximum seat height	6.35 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	10 ns
width	7.62 mm
Base Number Matches	1

Preview

Download Datasheet

View All

14 Pin DIP High Precision Triple Output TTL Compatible

Active Delay Lines

DELAY TIME

( nS )

5±1

6±1

7±1

8±1

9±1

10±1

11±1

12±1

13±1

14±1

15±1

16±1

17±1

18±1

PART

NUMBER

EPA1825-5

EPA1825-6

EPA1825-7

EPA1825-8

EPA1825-9

EPA1825-10

EPA1825-11

EPA1825-12

EPA1825-13

EPA1825-14

EPA1825-15

EPA1825-16

EPA1825-17

EPA1825-18

DELAY TIME

( nS )

19±1

20±1

21±1

22±1

23±1

24±1

25±1

30±1.5

35±1.5

40±1.5

45±2

50±2

55±2

60±2

PART

NUMBER

EPA1825-19

EPA1825-20

EPA1825-21

EPA1825-22

EPA1825-23

EPA1825-24

EPA1825-25

EPA1825-30

EPA1825-35

EPA1825-40

EPA1825-45

EPA1825-50

EPA1825-55

EPA1825-60

DELAY TIME

( nS )

65±2.5

70±2.5

75±2.5

80±2.5

85±3

90±3

95±3

100±3

125±4

150±4.5

175±5

200±6

225±7

250±8

PART

NUMBER

EPA1825-65

EPA1825-70

EPA1825-75

EPA1825-80

EPA1825-85

EPA1825-90

EPA1825-95

EPA1825-100

EPA1825-125

EPA1825-150

EPA1825-175

EPA1825-200

EPA1825-225

EPA1825-250

Delay Times referenced from input to leading edges at 25°C, 5.0V, with no load.

DC Electrical Characteristics

Parameter

Test Conditions

VCC = min. VIL = max. I OH = max

VCC = min. VIH = min. I OL= max

VCC = min. II = IIK

VCC = max. VIN = 2.7V

VCC = max. VIN = 5.25V

IIL

Low-Level Input Current

VCC = max. VIN = 0.5V

IOS Short Circuit Output Current VCC = max. VOUT = 0.

(One output at a time)

ICCH High-Level Supply Current

VCC = max. VIN = OPEN

ICCL Low-Level Supply Current

VCC = max. VIN = 0

TRO Output Rise Time

≤

500 nS (0.75 to 2.4 Volts)

Fanout High-Level Output

VCC = max. VOH = 2.7V

Fanout Low-Level Output

VCC = max. VOL = 0.5V

VOH

VOL

VIK

IIH

High-Level Output Voltage

Low-Level Output Voltage

Input Clamp Voltage

High-Level Input Current

Schematic

Min Max Unit

2.7

0.5

-1.2V

1.0

-2

-100

µA

VCC

-40

115

20 TTL LOAD

10 TTL LOAD

7 GROUND

Recommended

Operating Conditions

VCC

VIH

VIL

IIK

IOH

IOL

PW*

Supply Voltage

High-Level Input Voltage

Low-Level Input Voltage

Input Clamp Current

High-Level Output Current

Low-Level Output Current

Pulse Width of Total Delay

Duty Cycle

Operating Free-Air Temperature

Package Dimensions

Min

4.75

2.0

Max

5.25

0.8

-18

-1.0

Unit

°C

PCA

EPA1825-5

Date Code

White Dot

Pin#1

.280

Max.

+70

.780 Max.

.020

Min.

.010

Typ.

.365

Max.

*These two values are inter-dependent.

.250

Max.

Input Pulse Test Conditions @ 25° C

EIN

TRI

PRR

VCC

Pulse Input Voltage

Pulse Width % of Total Delay

Pulse Rise Time (0.75 - 2.4 Volts)

Pulse Repetition Rate @ Td

≤

200 nS

Pulse Repetition Rate @ Td > 200 nS

Supply Voltage

3.2

110

2.0

1.0

100

5.0

Unit

Volts

MHz

KHz

Volts

.020

Typ.

.120 Min.

.200

DSA1825 8/25/94

QAF-CSO1 Rev. B 8/25/94

Unless Otherwise Noted Dimensions in Inches

Tolerances:

Fractional = ± 1/32

.XX = ± .030

.XXX = ± .010

ELECTRONICS

INC.

16799 SCHOENBORN ST.

NORTH HILLS, CA 91343

TEL: (818) 892-0761

FAX: (818) 894-5791

Recommended Resources

337 basic working circuit

B7430 (former Soviet Union) type socket electrical wiring diagram circuit

STR80145 application circuit diagram c

Cordless phone overvoltage protection circuit

Tube amplifier CS8420 circuit diagram

Interface and program design between digital potentiometer X9241 and PIC microcontroller

Let me share the application information about sim300 obtained from the school intranet database!: Let me share the application information about sim300 obtained from the school intranet database!...; sinoxu MCU

Localization: [size=14px]Which domestic FPGA can replace EP3C25E144I7[/size]...; y2018y FPGA/CPLD

MSP430 Development Summary: 1. #i nclude means to be in the editor setting directory, #i nclude "" means to be in the current project directory. 2. To call a function in another file, put the function file in the current project...; oyzw111 Microcontroller MCU

Op Amp Stability - (Part 5 and 6): [i=s] This post was last edited by dontium on 2015-1-23 12:49 [/i] Part 5 - Practical Design of Single Supply Buffers Part 6 - Capacitive Load Stability...; Littleshook Analogue and Mixed Signal

[MSP430 Weekly Review 2] Review of the SEED-EXP430F5529 development board and the rapidly expanding resource library: Two weeks have passed since the TI MSP430F5529 training [Study with courtesy], and only two netizens on the forum have completed the training and received the development board. The winners of the fir...; wstt Microcontroller MCU

Application Analysis II: Synchronous Digital Writing While Reading Analog Data: To achieve simultaneous digital writing while reading analog data [1] , follow these steps: 1.Use any given entry in a channel gain queue 2.Take the digital data and then mask all unused bits by perfo...; Jack_ma Test/Measurement

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components