MOSEL VITELIC
MS7200L/7201AL/7202AL
256 x 9, 512 x 9, 1K x 9
CMOS FIFO
Descriptions
MS7200L/7201AL/7202AL
Features
s
First-In/First-Out static RAM based dual port
memory
s
Three densities in a x9 configuration
s
Low power versions
s
Includes empty, full, and half full status flags
s
Direct replacement for industry standard
Mostek and IDT
s
Ultra high-speed 30 MHz FIFOs available with
33 ns cycle times.
s
Fully expandable in both depth and width
s
Simultaneous and asynchronous read and write
s
Auto retransmit capability
s
TTL compatible interface, single 5V ± 10%
power supply
s
Available in 28 pin 300 mil and 600 mil plastic
DIP, 32 Pin PLCC and 330 mil SOG
Pin Configurations
28-PIN PDIP
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
Q3
Q8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
V
CC
D4
D5
D6
D7
FL / RT
RS
EF
The MS7200L/7201AL/7202AL are dual-port
static RAM based CMOS First-In/First-Out (FIFO)
memories organized in nine-bit wide words. The
devices are configured so that data is read out in
the same sequential order that it was written in.
Additional expansion logic is provided to allow for
unlimited expansion of both word size and depth.
The dual-port RAM array is internally sequenced
by independent Read and Write pointers with no
external addressing needed. Read and write
operations are fully asynchronous and may occur
simultaneously, even with the device operating at
full speed. Status flags are provided for full, empty,
and half-full conditions to eliminate data underflow
and overflow. The x9 architecture provides an
additional bit which may be used as a parity or
control bit. In addition, the devices offer a retransmit
capability which resets the Read pointer and allows
for retransmission from the beginning of the data.
The MS7200L/7201AL/7202AL are available in a
range of frequencies from 10 to 30 MHz (33 - 100 ns
cycle times). A low power version with a 500µA
power down supply current is available. They are
manufactured on Mosel-Vitelic’s high performance
1.2µ CMOS process and operate from a single 5V
power supply.
300 mil
600 mil
DIP
&
330 mil
SOG
Block Diagram
DATA INPUTS (Q0-Q8)
22
21
20
19
18
17
16
15
XO / HF
Q7
Q6
Q5
Q4
R
W
WRITE
CONTROL
WRITE
POINTER
RAM
ARRAY
256x9
512x9
1Kx9
READ
POINTER
32-PIN PLCC
VCC
D4
THREE
STATE
BUFFERS
DATA OUTPUTS (Q0-Q8)
29
28
27
26
25
24
23
22
21
D6
D7
NC
FL / RT
RS
EF
XO / HF
Q7
Q6
NC
D3
D8
4
D2
D1
D0
XI
FF
Q0
Q1
NC
Q2
5
8
7
8
9
10
11
14
13
3
2
1 32 31 30
D5
W
R
READ
CONTROL
RESET
LOGIC
FLAG
LOGIC
EF
HF
FF
RS
FL / RT
32 Pin PLCC
Top View
14 15 16 17 18 19 20
VSS
NC
XI
EXPANSION
LOGIC
Q8
R
Q4
Q3
Q5
XO
MS7200L/01AL/02AL Rev. 1.0 January 1995
1
MOSEL VITELIC
Signal Descriptions
INPUTS:
Data In (D
0
- D
8
)
These data inputs accept 9-bit data words for
sequential storage in the FIFO during write
operations.
CONTROLS:
Reset (RS)
The reset input is active LOW. When asserted,
the device is asynchronously reset, and both the
read and write internal pointers are set to the first
location in the FIFO. A Reset is required after
power-up before a write operation can occur. Both
Read Enable (R) and Write Enable (W) must be
HIGH during Reset.
Read Enable (R)
The read enable input is active LOW. As long as
the Empty Flag (EF) is not set, the read cycle is
started on the falling edge of this signal. The data is
accessed on a First-In/First-Out basis, independent
of any write activity, and is presented on the Data
Output pins (Q0 - Q8). When
R
goes HIGH the Data
Output pins return to the high impedance state, and
the read pointer is incremented. When the FIFO is
empty or all of the data has been read, the Empty
Flag will be set and further read operations are
inhibited until a valid write operation has been
performed.
Write Enable (W)
The write enable input is active LOW. As long as
the Full Flag (FF) is not set, the write cycle is started
on the falling edge of this signal. The data present
on the Data Input pins (D0 - D8) is stored
sequentially, independent of any read activity.
When
W
goes HIGH the write cycle is terminated
and the write pointer is incremented. When the
maximum capacity of the FIFO has been reached
the Full Flag will be set, and further write operations
are inhibited until a valid read operation has been
performed.
Expansion In (XI)
This input pin serves two purposes. When
grounded, it indicates that the device is being
operated in the single device mode. In Depth
Expansion mode, this pin is connected to the
Expansion Out Output (XO) of the previous device.
MS7200L/7201AL/7202AL
First Load/Retransmit (FL/RT)
This is a dual-purpose input. In single device
mode (when Expansion In (XI) is grounded) this pin
acts as the retransmit input. A LOW pulse on this
will reset the read pointer to the first memory
location of the FIFO. The write pointer is unaffected.
Both the read enable (R) and write enable (W)
inputs must remain HIGH during the retransmit
cycle.
In Depth Expansion mode this pin acts as a first
load indicator. It must be grounded on the first
device in the chain to indicate which device is the
first to receive data.
OUTPUTS:
Data Output (Q
0
- Q
8
)
A 9 bit data word from the FIFO is output on these
pins during read operations. They are in the high
impedance state whenever
R
is HIGH.
Empty Flag (EF)
This output is active LOW. When all of the data
has been read from the FIFO (defined as when the
Read pointer is one location behind the Write
pointer) this flag will be set. The Data Output pins
will be forced into the high impedance state, and all
further read operations will be inhibited until a valid
write operation has been performed (which will
reset this flag).
Full Flag (FF)
This output is active LOW. To prevent data
overflow, when the maximum capacity of the FIFO
has been reached (defined as when the Write
pointer is one location behind the Read pointer) this
flag will be set. All further write operations will be
inhibited until a valid read operation has been
performed (which will reset this flag).
Expansion Out/Half Full Flag (XO/HF)
This dual-purpose output is active LOW. In single
device mode (when Expansion In (XI) is grounded)
this flag will be set at the falling edge of the next
write operation after the FIFO has reached one-half
of its maximum capacity. This flag will remain set as
long as the difference between the read pointer and
the write pointer is greater than one-half of the
maximum capacity of the FIFO.
In Depth Expansion mode, this output is
connected to the Expansion In Input of the next
device in the chain. The Expansion Out pin
provides a pulse to the next device in the chain
when the last memory location has been reached.
2
MS7200L/01AL/02AL Rev. 1.0 January 1995
MOSEL VITELIC
Absolute Maximum Ratings
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
1.
Parameter
Terminal Voltage with
Repect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
-10 to +125
-60 to +150
1.0
20
°C
°C
W
mA
Condition
-0.5 to +7.0
Unit
V
Range
Commercial
MS7200L/7201AL/7202AL
Operating Range
Ambient
Temperature
0°C to + 70°C
Vcc
5V
±
10%
Capacitance
(1)
T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
Q
Parameter
Input Capacitance
Output Capacitance
Condition
V
IN
= 0V
V
DQ
= 0V
Max.
4
6
Unit
pF
pF
Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
DC Electrical Characteristics (over the commercial operating range)
Test
Parameter
V
IL
V
IH
I
IL
I
OL
V
OL
MS7200L/7201AL MS7200L/7201AL
7202AL
7202AL
(-25, -35)
(-50, -80)
Min. Typ. Max. Min. Typ. Max. Units
-
2.0
-1
-10
-
2.4
-
-
-
-
0.8
-
1
10
0.4
-
125
15
-
2.0
-1
-10
-
2.4
-
-
-
-
0.8
-
1
10
0.4
-
80
8
V
V
µA
µA
V
V
mA
mA
Parameter
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= Max, V
IN
= 0Vto V
CC
V
CC
= Max, R= V
IH
, V
IN
= 0V toV
CC
V
CC
= Min, I
OL
= 8mA
V
CC
= Min, I
OH
= -2mA
-
-
-
-
-
-
50
5
V
OH
I
CC1
I
CC2
I
CCSB(S)
Operating Power Supply Current V
CC
= Max, I
I/O
= 0mA, F = F
m ax
V
CC
= Max,
R
=
W
=
RS
=
FL
/
RT
=
Average Standby Current
V
IH
,
I
I/O
= 0mA
V
CC
= Max,
R
=
W
=
RS
=
FL
/
RT >
Power Down Power Supply
V
CC
-0.2V, V
IN
> V
CC
-0.2V or V
IN
<
Current (Standard Power)
Power Down Power Supply
Current (Low Power)
0.2V
V
CC
= Max,
R
=
W
=
RS
=
FL
/
RT
>
V
CC
-0.2V, V
IN
> V
CC
-0.2V or V
IN
<
0.2V
-
-
5
-
-
5
mA
I
CCSB(L)
-
-
500
-
-
500
µA
Truth Tables
Single Device Configuration/Width Expansion Mode
Mode
RS
Reset
Retransmit
0
1
Inputs
RT
X
0
XI
0
0
0
Internal Status
Read Pointer
Location Zero
Location Zero
Increment
(1)
Write Pointer
Location Zero
Unchanged
Increment
(1)
EF
0
X
X
Outputs
FF
1
X
X
HF
1
X
X
Read/Write
1
1
NOTE: 1. Pointer will increment if flag is high.
Depth Expansion/Compound Expansion Mode
Mode
RS
Reset-First Device
Reset all Other Devices
0
0
Inputs
FL
0
1
XI
(1)
(1)
Internal Status
Read Pointer
Location Zero
Location Zero
Write Pointer
Location Zero
Unchanged
EF
0
0
Outputs
FF
1
1
Read/Write
1
X
(1)
X
X
X
X
NOTE:
1.
XI
is connected to
XO
of previous device. See Figure 15.
RS
= Reset Input.
FL/RT
= First Load/Retransmit.
EF
= Empty Flag
Output.
FF
Full Flag Output.
XI
= Expansion Input.
MS7200L/01AL/02AL Rev. 1.0 January 1995
3
MOSEL VITELIC
MS7200L/7201AL/7202AL
MS7200L-25 MS7200L-35 MS7200L-50 MS7200L-80
MS7201AL-25 MS7201AL-35 MS7201AL-50 MS7201AL-80
MS7202AL-25 MS7202AL-35 MS7202AL-50 MS7202AL-80
Min.
Max. Min.
Max. Min.
Max. Min.
Max.
--
30
--
22.2
--
15
--
10
33
--
25
8
5
--
5
33
25
8
15
0
5
--
--
--
--
--
--
25
25
33
25
25
8
--
--
--
33
25
25
8
--
--
25
15
8
--
25
--
--
--
18
--
--
--
--
--
--
--
25
33
25
25
25
33
--
--
--
--
--
--
33
33
33
--
--
--
--
25
25
--
--
--
45
--
35
10
5
--
5
45
35
10
18
0
10
--
--
--
--
--
--
35
35
45
35
35
10
--
--
--
45
35
35
10
--
--
35
15
10
--
35
--
--
--
20
--
--
--
--
--
--
--
30
45
30
30
30
45
--
--
--
--
--
--
45
45
45
--
--
--
--
35
35
--
--
--
65
--
50
15
10
--
5
65
50
15
30
5
15
--
--
--
--
--
--
50
50
65
50
50
15
--
--
--
65
50
50
15
--
--
50
15
10
--
50
--
--
--
30
--
--
--
--
--
--
--
45
65
45
45
45
65
--
--
--
--
--
--
65
65
65
--
--
--
--
50
50
--
--
--
100
--
80
20
10
--
5
100
80
20
40
10
20
--
--
--
--
--
--
80
80
100
80
80
20
--
--
--
100
80
80
20
--
--
80
15
10
--
80
--
--
--
30
--
--
--
--
--
--
--
60
100
60
60
60
100
--
--
--
--
--
--
100
100
100
--
--
--
--
80
80
--
--
--
AC Electrical Characteristics (over the commercial operating range)
Parameter
Name
Parameter
ƒ
S
Shift Frequency
Read Cycle
t
RC
Read Cycle Time
t
A
Access Time
t
RPW
Read Pulse Width
t
RR
Read Recovery Time
(2)
t
RLZ
Read Pulse Low to Data Bus at Low Z
(2,3)
t
RHZ
Read Pulse High to Data Bus at High Z
t
DV
Data Valid from Read Pulse High
Write Cycle
t
WC
Write Cycle Time
(1)
t
WPW
Write Pulse Width
t
WR
Write Recovery Time
t
DS
Data Setup Time
t
DH
Data Hold Time
t
WLZ(2,3)
Write Pulse High to Data Bus at Low Z
Flag Timing
t
REF
Read Low to Empty Flag Low
t
RHF
Read High to Half Full Flag High
t
RFF
Read High to Full Flag High
t
WEF
Write High to Empty Flag High
t
WFF
Write Low to Full Flag Low
t
WHF
Write Low to Half Full Flag Low
t
RPE
Read Pulse Width After EF High
t
WPF
Write Pulse Width After
FF
High
Reset Timing
t
RSC
Reset Cycle Time
t
RS (1)
Reset Pulse Width
t
RSS
Reset Set Up Time
t
RSR
Reset Recovery Time
t
EFL
Reset to Empty Flag Low
t
HFH
Reset to Half Full Flag High
t
FFH
Reset to Full Flag High
Retransmit Timing
t
RTC
Retransmit Cycle Time
(1)
t
RT
Retransmit Pulse Width
t
RTS
Retransmit Set up Time
t
RTR
Retransmit Recovery Time
Expansion Timing
t
XOL
Read/Write to
XO
Low
t
XOH
Read/Write to
XO
High
t
XI
XI
Pulse Width
t
XIS
XI
Set up Time
t
XIR
XI
Recovery Time
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Pulse widths less than minimum value are not allowed.
2. Values guaranteed by design, not currently tested.
3. Only applies to read data flow-through mode.
MS7200L/01AL/02AL Rev. 1.0 January 1995
4
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