935281128551 datasheet, PDF - EEWORLD Datasheet

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935281128551: DescriptionLVC/LCX/Z SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PBGA56, 4.50 X 7 MM, 0.65 MM PITCH, PLASTIC, MO-225, SOT702-1, VFBGA-56; Categorylogic logic; File Size148KB，20 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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935281128551 Overview

LVC/LCX/Z SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PBGA56, 4.50 X 7 MM, 0.65 MM PITCH, PLASTIC, MO-225, SOT702-1, VFBGA-56

935281128551 Parametric

Parameter Name	Attribute value
Maker	NXP
package instruction	VFBGA,
Reach Compliance Code	unknown
Other features	WITH DIRECTION CONTROL
series	LVC/LCX/Z
JESD-30 code	R-PBGA-B56
JESD-609 code	e0
length	7 mm
Logic integrated circuit type	BUS TRANSCEIVER
Number of digits	8
Number of functions	2
Number of ports	2
Number of terminals	56
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
propagation delay (tpd)	6 ns
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	0.65 mm
Terminal location	BOTTOM
width	4.5 mm

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74LVC16245A; 74LVCH16245A

16-bit bus transceiver with direction pin; 5 V tolerant; 3-state

Rev. 11 — 8 December 2011

Product data sheet

1. General description

The 74LVC16245A; 74LVCH16245A are 16-bit transceivers featuring non-inverting

3-state bus compatible outputs in both send and receive directions. The device features

two output enable (nOE) inputs for easy cascading and two send/receive (nDIR) inputs for

direction control. nOE controls the outputs so that the buses are effectively isolated. This

device can be used as two 8-bit transceivers or one 16-bit transceiver.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices in mixed

3.3 V and 5 V applications.

The 74LVCH16245A bus hold on data inputs eliminates the need for external pull-up

resistors to hold unused inputs.

2. Features and benefits



5 V tolerant inputs/outputs for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

MULTIBYTE flow-through standard pin-out architecture

Low inductance multiple power and ground pins for minimum noise and ground

bounce

Direct interface with TTL levels

High-impedance when V

= 0 V

All data inputs have bus hold (74LVCH16245A only)

Complies with JEDEC standard:



JESD8-7A (1.65 V to 1.95 V)



JESD8-5A (2.3 V to 2.7 V)



JESD8-C/JESD36 (2.7 V to 3.6 V)

ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-B exceeds 200 V



CDM JESD22-C101E exceeds 1000 V

Specified from

40 C

to +85

C

and

40 C

to +125

C



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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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