June 2005
rev 1.0
Low Voltage 1:18 Clock Distribution Chip
Features
ASM2I9940L
With low output impedance (≈20Ω), in both the HIGH and
LVPECL or LVCMOS Clock Input
2.5V LVCMOS Outputs for Pentium II
Microprocessor Support*
150pS Maximum Output-to-Output Skew
Maximum Output Frequency of 250MHz
32 Lead LQFP & TQFP Packaging
Dual or Single Supply Device:
Dual V
CC
Supply Voltage, 3.3V Core and
2.5V Output
Single 3.3V V
CC
Supply Voltage for 3.3V
Outputs
Single 2.5V V
CC
Supply Voltage for 2.5V I/O
Pin and Function compatible to MPC940L,
MPC9109, CY29940 and CY29940-1
LOW logic states, the output buffers of the ASM2I9940L
are ideal for driving series terminated transmission lines.
With a 20Ω output impedance the ASM2I9940L has the
capability of driving two series terminated lines from each
output. This gives the device an effective fanout of 1:36.
The differential LVPECL inputs of the ASM2I9940L allow
the device to interface directly with a LVPECL fanout buffer
to build very wide clock fanout trees or to couple to a high
frequency clock source. The LVCMOS input provides a
more standard interface for applications requiring only a
single clock distribution chip at relatively low frequencies. In
addition, the two clock sources can be used to provide for a
test clock interface as well as the primary system clock. A
logic HIGH on the LVCMOS_CLK_Sel pin will select the
LVCMOS level clock input. All inputs of the ASM2I9940L
have internal
pullup/pulldown resistor, so they can be left
open if unused.
The ASM2I9940L is a single or dual supply device. The
device power supply offers a high degree of flexibility. The
device can operate with a 3.3V core and 3.3V output, a
3.3V core and 2.5V outputs as well as a 2.5V core and
2.5V outputs. The 32-lead LQFP and TQFP Packages
were chosen to optimize performance, board space and
cost of the device. The 32-lead LQFP and TQFP Packages
have a 7x7mm
2
body size with conservative 0.8mm pin
spacing.
Functional Description
The ASM2I9940L is a 1:18 low Voltage Clock distribution
chip with 2.5V or 3.3V LVCMOS output capabilities. The
device features the capability to select either a differential
LVPECL or LVCMOS compatible input. The 18 outputs are
2.5V or 3.3V LVCMOS compatible and feature the drive
strength to drive 50Ω series or parallel terminated
transmission lines. With output-to-output skews of 150pS,
the ASM2I9940L is ideal as a clock distribution chip for the
most demanding of Synchronous systems. The 2.5V
outputs also make the device ideal for supplying clocks for
a high performance microprocessor based design.
* Pentium II is a trademark of Intel Corporation
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
June 2005
rev 1.0
Table 3. Pin Configurations
Pin #
5
6
3
4
32,31,30,28,27,26,24,23,22,
20,19,18,15,14,13,11,10,9
2
1,12,17,25
7,21
8, 16,29
ASM2I9940L
Pin Name
PECL_CLK
PECL_CLK
LVCMOS_CLK
LVCMOS_CLK_Sel
Q0–Q17
GNDI
GNDO
V
CCI
V
CCO
I/O
Input
Input
Input
Output
Type
LVPECL
LVCMOS
LVCMOS
LVCMOS
Supply
Supply
Supply
Supply
Function
LVPECL Clock Inputs
LVCMOS Clock Input
Selects either LVPECL or
LVCMOS input as Clock Source
Clock Outputs
Core Negative Power Supply
Output Negative Power Supply
Core Positive Power Supply
Output Positive Power Supply
Table 4. Absolute Maximum Ratings
1
Symbol
V
CC
V
I
I
IN
T
Stor
T
s
T
DV
Supply Voltage
Input Voltage
Input Current
Storage Temperature Range
Max. Soldering Temperature (10 sec)
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
Parameter
Min
–0.3
–0.3
–40
Max
3.6
V
CC
+ 0.3
±20
125
260
2
Unit
V
V
mA
°C
°C
KV
Note:1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
3 of 13
June 2005
rev 1.0
Table 5. DC Characteristics
(T
A
= 0° to 70°C, V
CCI
= 3.3V ± 5%, V
CCO
= 3.3V ± 5%
Symbol
V
IH
V
IL
V
PP
V
CMR
V
OH
V
OL
I
IN
C
IN
C
pd
Z
OUT
I
CC
)
ASM2I9940L
Characteristic
Input HIGH Voltage
Input LOW Voltage
Peak–to–Peak Input
Voltage
Common Mode Range
Output HIGH Voltage
Output LOW Voltage
Input Current
Input Capacitance
Power Dissipation Capacitance
Output Impedance
Maximum Quiescent Supply Current
CMOS_CLK
CMOS_CLK
PECL_CLK
PECL_CLK
Min
2.4
500
V
CC
–1.4
2.4
Typ
Max
V
CCI
0.8
1000
V
CC
–0.6
0.5
±200
Unit
V
V
mV
V
V
V
µA
pF
pF
Condition
I
OH
= –20mA
I
OH
= 20mA
4.0
10
18
23
0.5
28
1.0
per output
Ω
mA
Table 6. AC Characteristics
(T
A
= 0° to 70°C, V
CCI
= 3.3V ± 5%, V
CCO
= 3.3V ± 5%)
Symbol
F
max
t
PLH
t
PLH
t
sk(o)
t
sk(pp)
t
sk(pp)
t
sk(pp)
DC
t
r
, t
f
Part-to-Part Skew
Part-to-Part Skew
Part-to-Part Skew
Output Duty Cycle
Output Rise/Fall Time
Characteristic
Maximum Input Frequency
Propagation Delay
Propagation Delay
Output-to-output Skew
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
PECL_CLK
CMOS_CLK
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
PECL_CLK CMOS_CLK
f
CLK
< 134 MHz
f
CLK
<250 MHz
Min
2.0
1.7
2.0
1.8
Typ
2.7
2.5
2.9
2.5
Max
250
3.4
3.0
3.7
3.2
150
150
1.5
1.3
1.8
1.5
850
750
55
60
1.1
Unit
MHz
nS
nS
pS
nS
nS
pS
%
%
nS
Condition
Note
1
.
Note
1
.
Notes
1,2
Notes
1,2
Notes
1,3
45
40
0.3
50
50
Input DC = 50%
Input DC = 50%
0.5 – 2.4 V
Note: 1. Tested using standard input levels, Production tested @ 150MHz.
2. Across temperature and voltage ranges, includes output skew.
3. For a specific temperature and voltage, includes output skew.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
4 of 13
June 2005
rev 1.0
Table 7. DC Characteristics
(T
A
= 0° to 70°C, V
CCI
= 3.3V ± 5%, V
CCO
= 2.5V ± 5%)
Symbol
V
IH
V
IL
V
PP
V
CMR
V
OH
V
OL
I
IN
C
IN
C
pd
Z
OUT
I
CC
ASM2I9940L
Characteristic
Input HIGH Voltage
Input LOW Voltage
Peak–to–Peak Input
Voltage
Common Mode Range
Output HIGH Voltage
Output LOW Voltage
Input Current
Input Capacitance
Power Dissipation Capacitance
Output Impedance
Maximum Quiescent Supply Current
CMOS_CLK
CMOS_CLK
PECL_CLK
PECL_CLK
Min
2.4
500
V
CC
–1.4
1.8
Typ
Max
V
CCI
0.8
1000
V
CC
–0.6
0.5
±200
Unit
V
V
mV
V
V
V
µA
pF
pF
Ω
Condition
I
OH
= –20mA
I
OH
= 20mA
4.0
10
23
0.5
1.0
per output
mA
Table 8. AC Characteristics
(T
A
= 0° to 70°C, V
CCI
= 3.3V ± 5%, V
CCO
= 2.5V ± 5% )
Symbol
F
max
t
PLH
t
PLH
t
sk(o)
t
sk(pp)
t
sk(pp)
t
sk(pp)
DC
t
r
, t
f
Part–to–Part Skew
Part–to–Part Skew
Part–to–Part Skew
Output Duty Cycle
Output Rise/Fall Time
Characteristic
Maximum Input Frequency
Propagation Delay
Propagation Delay
Output-to-output Skew
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
PECL_CLK
CMOS_CLK
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
PECL_CLK CMOS_CLK
f
CLK
< 134 MHz
f
CLK
<250 MHz
Min
2.0
1.7
2.0
1.8
Typ
2.8
2.5
2.9
2.5
Max
250
3.5
3.0
3.8
3.3
150
150
1.5
1.3
1.8
1.5
850
750
55
60
1.2
Unit
MHz
nS
nS
pS
nS
nS
pS
%
%
nS
Condition
Note
1
.
Note
1
Notes
1,2
Notes
1,2
Notes
1,3
45
40
0.3
50
50
Input DC = 50%
Input DC = 50%
0.5 – 1.8 V
Note: 1.Tested using standard input levels, Production tested @ 150MHz.
2. Across temperature and voltage ranges, includes output skew.
3. For a specific temperature and voltage, includes output skew.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
5 of 13
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