device ideal for supplying clocks for a high performance
Pentium II
TM
microprocessor based design.
With a low output impedance (≈12Ω), in both the HIGH and
LOW logic states, the output buffers of the ASM2I9942C
are ideal for driving series terminated transmission lines.
With an output impedance of 12Ω, the ASM2I9942C can
drive two series terminated transmission lines from each
output. This capability gives the ASM2I9942C an effective
fanout of 1:36. The ASM2I9942C provides enough copies
of low skew clocks for most high performance synchronous
systems.
The LVCMOS/LVTTL input of the ASM2I9942C provides a
more standard LVCMOS interface. The OE pins will place
the outputs into a high impedance state. The OE pin has an
internal pullup resistor.
The ASM2I9942C is a single supply device. The V
CC
power
pins require either 2.5V or 3.3V. The 32–lead TQFP and
LQFP package is chosen to optimize performance, board
space and cost of the device. The 32–lead TQFP has a
7x7mm
2
body size with a conservative 0.8mm pin spacing.
Microprocessor Support
150pS Maximum Targeted Output–to–Output Skew
Maximum Output Frequency of 250MHz @ 3.3 V
CC
32–Lead TQFP and LQFP Packaging
Single 3.3V or 2.5V Supply.
Pin and Function compatible to MPC942C
.
Functional Description
The ASM2I9942C is a 1:18 low voltage clock distribution
chip with 2.5V or 3.3V LVCMOS output capabilities. The
device is offered in two versions; the ASM2I9942C has an
LVCMOS input clock while the ASM2I9942P has an
LVPECL input clock. The 18 outputs are 2.5V or 3.3V
LVCMOS compatible and feature the drive strength to drive
50Ω series or parallel terminated transmission lines. With
output–to–output skews of 200pS, the ASM2I9942C is
ideal as a clock distribution chip for the most demanding of
synchronous systems. The 2.5V outputs also make the
*Pentium II is a trademark of Intel Corporation
Alliance Semiconductor
2575, Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
May 2005
rev 0.2
Block Diagram
Q0
LVCMOS_CLK
Q1:Q16
Q17
OE
(Int. Pullup)
ASM2I9942C
Table 1. Function Table
OE
0
1
Output
HIGH IMPEDANCE
OUTPUTS ENABLED
24
GND
Q5
Q4
Q3
VCC
Q2
Q1
Q0
25
26
27
28
29
30
31
32
1
23
22
21
20
19
18
GND
17
16
15
14
VCC
Q12
Q13
Q14
GND
Q15
Q16
Q17
13
12
11
10
9
8
VCC
VCC
Q10
6
NC
ASM2I9942C
2
3
4
5
LVCMOS_CLK
GND
GND
OE
NC
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
VCC
Q11
7
Pin Diagram
Q6
Q7
Q8
Q9
2 of 10
May 2005
rev 0.2
Table 2. Pin Configuration
Pin #
1,2,12,17,25
3
4,6
5
7,8,16,21,29
9-11
13-15
18-20
22-24
26-28
30-32
ASM2I9942C
Pin Name
GND
LVCMOS_CLK
NC
OE
VCC
Q17-Q15
Q14-Q12
Q11-Q9
Q8-Q6
Q5-Q3
Q2-Q0
I/O
Supply
Input
-
Input
Supply
Output
Output
Output
Output
Output
Output
Type
Ground
LVCMOS
-
LVCMOS
VCC
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Function
LVCMOS Clock Input
No Connect
Outputs are enabled, when OE is
high and are tri-stated, when OE is
made low.
Positive power supply
Clock outputs
Clock outputs
Clock outputs
Clock outputs
Clock outputs
Clock outputs
Table 3. Absolute Maximum Rating
1
Symbol
V
CC
V
I
I
IN
T
Stor
Supply Voltage
Input Voltage
Input Current
Storage Temperature Range
Parameter
Min
–0.3
–0.3
–40
Max
3.6
V
CC
+ 0.3
±20
125
Unit
V
V
mA
°C
Note: 1These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Table 4. DC Characteristics
(T
A
= 0°to 70°C, V
CC
= 2.5V ± 5%)
Symbol
V
IH
V
IL
V
OH
V
OL
I
IN
C
IN
C
PD
Z
OUT
I
CC
Characteristic
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input Current
Input Capacitance
Power Dissipation Capacitance
Output Impedance
Maximum Quiescent Supply Current
Min
2.0
2.0
Typ
Max
V
CCI
0.8
0.5
±200
Unit
V
V
V
V
µA
pF
pF
Ω
mA
Condition
I
OH
= –16 mA
I
OL
= 16 mA
4.0
14
12
0.5
Per Output
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
3 of 10
May 2005
rev 0.2
Table 5. AC Characteristics
(T
A
= 0°to 70°C, V
CC
= 2.5V ± 5%)
Symbol
F
max
t
PLH
ASM2I9942C
Characteristic
Maximum Frequency
Propagation Delay
1
Output-to-output Skew
Within one bank
Min
1.5
Typ
Max
200
2.8
150
Unit
MHz
nS
Condition
pS
350
1.3
600
45
0.2
55
1.0
nS
pS
%
nS
t
sk
(o)
t
sk
(pr)
t
sk
(pr)
d
t
t
r
, t
f
Any output, Any Bank
Part–to–Part Skew
1, 2
Part–to–Part Skew
1, 3
Duty Cycle
Output Rise/Fall Time
Note: 1.Tested using standard input levels, production tested @ 133 MHz.
2.Across temperature and voltage ranges, includes output skew.
3.For a specific temperature and voltage, includes output skew.
Table 6. DC Characteristics
(T
A
= 0°to 70°C, V
CC
= 3.3V ± 5%)
Symbol
V
IH
V
IL
V
OH
V
OL
I
IN
C
IN
C
PD
Z
OUT
I
CC
Characteristic
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input Current
Input Capacitance
Power Dissipation Capacitance
Output Impedance
Maximum Quiescent Supply Current
Min
2.4
2.4
Typ
Max
V
CCI
0.8
0.5
±200
Unit
V
V
V
V
µA
pF
pF
Ω
mA
Condition
I
OH
= –20 mA
I
OL
= 20 mA
4.0
14
12
0.5
Per Output
Table 7. AC Characteristics
(T
A
= 0°to 70°C, V
CC
= 3.3V ± 5%)
Symbol
F
max
t
PLH
Characteristic
Maximum Frequency
Propagation Delay
1
Min
1.3
Typ
Max
250
2.3
150
Unit
MHz
nS
Condition
t
sk(o)
Output-to-output Skew
Within one bank
Any Output, Any Bank
pS
350
1.0
500
45
0.2
55
1.0
nS
pS
%
nS
t
sk(pr)
t
sk(pr)
d
t
t
r
, t
f
Part–to–Part Skew
Part–to–Part Skew
Duty Cycle
1,2
1,3
Output Rise/Fall Time
Note: 1.Tested using standard input levels, production tested @ 133 MHz.
2. Across temperature and voltage ranges, includes output skew.
3. For a specific temperature and voltage, includes output skew.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
4 of 10
May 2005
rev 0.2
Power Consumption of the ASM2I9942C and
Thermal Management
The ASM2I9942C AC specification is guaranteed for the
entire operating frequency range up to 250MHz. The
ASM2I9942C power consumption and the associated
long-term
reliability
may
decrease
the
maximum
frequency limit, depending on operating conditions such
as clock frequency, supply voltage, output loading,
ambient temperature, vertical convection and thermal
conductivity
of
package
and
board.
This
section
describes the impact of these parameters on the junction
temperature and gives a guideline to estimate the
ASM2I9942C
die
junction
temperature
and
the
associated device reliability.
ASM2I9942C
Where I
CCQ
is the static current consumption of the
ASM2I9942C, C
PD
is the power dissipation capacitance
per output,
(Μ)Σ
C
L
represents the external capacitive
output load, N is the number of active outputs (N is
always
12
in
case
of
the
ASM2I9942C).
The
ASM2I9942C supports driving transmission lines to
maintain high signal integrity and tight timing parameters.
Any transmission line will hide the lumped capacitive load
at the end of the board trace, therefore,
Σ
C
L
is zero for
controlled
transmission
line
systems
and
can
be
eliminated from equation 1. Using parallel termination
output termination results in equation 2 for power
dissipation.
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination. V
OL
, I
OL
, V
OH
and I
OH
are
a function of the output termination technique and DC
Q
is
the clock signal duty cycle. If transmission lines are used
Table 8. Die junction temperature and MTBF
Junction temperature (°C)
100
110
120
130
MTBF (Years)
20.4
9.1
4.2
2.0
Σ
C
L
is zero in equation 2 and can be eliminated. In
general,
the
use
of
controlled
transmission
line
techniques eliminates the impact of the lumped capacitive
loads at the end lines and greatly reduces the power
dissipation of the device. Equation 3 describes the die
junction temperature T
J
as a function of the power
consumption.
Where R
thja
is the thermal impedance of the package
(junction to ambient) and T
A
is the ambient temperature.
According to Table 8, the junction temperature can be
used to estimate the long-term device reliability. Further,
combining equation 1 and equation 2 results in a
maximum operating frequency for the ASM2I9942C in a
series terminated transmission line system, equation 4.
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable
MTBF, the die junction temperature of the ASM2I9942C
needs to be controlled and the thermal impedance of the
board/package
dissipated
equation1.
in
should
the
be
optimized.
is
The
power
in
ASM2I9942C
represented
P
TOT
=
I
CCQ
+
V
CC
⋅
f
CLOCK
⋅
N
⋅
C
PD
+
∑
C
L
⋅
V
CC
M
P
TOT
=
V
CC
⋅
I
CCQ
+
V
CC
⋅
f
CLOCK
⋅
N
⋅
C
PD
+
∑
C
L
+
∑
DC
Q
⋅
I
OH
(
V
CC
−
V
OH
)
+
(
1
−
DC
Q
)
⋅
I
OL
⋅
V
OL
M
P
T
J
=
T
A
+
P
TOT
⋅
R
thja
Equation
1
[
]
Equation
2
Equation
3
Equation
4
f
CLOCKMAX
=
1
2
C
PD
⋅
N
⋅
V
CC
T
−
T
A
⋅
J
,
MAX
−
(
I
CCQ
⋅
V
CC
)
R
thja
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
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