Datasheet
μ
PD44164184B
18M-BIT DDR II SRAM
4-WORD BURST OPERATION
Description
The
μ
PD44164184B is a 1,048,576-word by 18-bit synchronous double data rate static RAM fabricated with
advanced CMOS technology using full CMOS six-transistor memory cell.
The
μ
PD44164184B integrate unique synchronous peripheral circuitry and a burst counter. All input
registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage,
high density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
R10DS0015EJ0200
Rev.2.00
October 6, 2011
Features
•
1.8
±
0.1 V power supply
•
165-pin PLASTIC BGA (13 x 15)
•
HSTL interface
•
PLL circuitry for wide output data valid window and future frequency scaling
•
Pipelined double data rate operation
•
Common data input/output bus
•
Two-tick burst for low DDR transaction size
•
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
•
Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
•
Internally self-timed write control
•
Clock-stop capability. Normal operation is restored in 20
μ
s after clock is resumed.
•
User programmable impedance output (35 to 70
Ω)
•
Fast clock cycle time : 3.3 ns (300 MHz), 3.5 ns (287 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
•
Simple control logic for easy depth expansion
•
JTAG 1149.1 compatible test access port
R10DS0015EJ0200 Rev.2.00
October 6, 2011
Page 1 of 32
μ
PD44164184B
Ordering Information
Organizatio
n
(word x bit)
1M x 18
Cycle
time
3.3ns
3.5ns
4.0ns
5.0ns
1M x 18
3.3ns
3.5ns
4.0ns
5.0ns
1M x 18
3.3ns
3.5ns
4.0ns
5.0ns
1M x 18
3.3ns
3.5ns
4.0ns
5.0ns
Clock
frequency
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
Ta =
−40
to 85°C
Ta =
−40
to 85°C
Ta = 0 to 70°C
Operating Ambient
Temperature
Ta = 0 to 70°C
Part No.
Package
165-pin
PLASTIC BGA
(13 x 15)
Lead-free
165-pin
PLASTIC BGA
(13 x 15)
Lead
165-pin
PLASTIC BGA
(13 x 15)
Lead-free
165-pin
PLASTIC BGA
(13 x 15)
Lead
μ
PD44164184BF5-E33-EQ3-A
μ
PD44164184BF5-E35-EQ3-A
μ
PD44164184BF5-E40-EQ3-A
μ
PD44164184BF5-E50-EQ3-A
μ
PD44164184BF5-E33-EQ3
μ
PD44164184BF5-E35-EQ3
μ
PD44164184BF5-E40-EQ3
μ
PD44164184BF5-E50-EQ3
μ
PD44164184BF5-E33Y-EQ3-A
μ
PD44164184BF5-E35Y-EQ3-A
μ
PD44164184BF5-E40Y-EQ3-A
μ
PD44164184BF5-E50Y-EQ3-A
μ
PD44164184BF5-E33Y-EQ3
μ
PD44164184BF5-E35Y-EQ3
μ
PD44164184BF5-E40Y-EQ3
μ
PD44164184BF5-E50Y-EQ3
R10DS0015EJ0200 Rev.2.00
October 6, 2011
Page 2 of 32
μ
PD44164184B
Pin Arrangement
165-pin PLASTIC BGA (13 x 15)
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/72M
3
A
NC
NC
DQ10
DQ11
NC
DQ13
V
DD
Q
NC
DQ14
NC
NC
DQ16
DQ17
A
4
R, W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
BW1#
NC/288M
6
K#
K
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC/144M
8
LD#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
V
SS
/36M
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
BW0#
A1
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
A0, A1, A
DQ0 to DQ17
LD#
R, W#
BW0#, BW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
Remarks 1.
2.
3.
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
×××#
indicates active LOW.
Refer to
Package Dimensions
for the index mark.
2A, 7A, 10A and 5B are expansion addresses
: 10A for 36Mb
: 10A and 2A for 72Mb
: 10A, 2A and 7A for 144Mb
: 10A, 2A, 7A and 5B for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0015EJ0200 Rev.2.00
October 6, 2011
Page 3 of 32
μ
PD44164184B
Pin Description
(1/2)
Symbol
A0
A1
A
Type
Input
Description
Synchronous Address Inputs: These inputs are registered and must meet the setup
and hold times around the rising edge of K. All transactions operate on a burst of four
words (two clock periods of bus activity). A0 and A1 are used as the lowest two
address bits for BURST READ and BURST WRITE operations permitting a random
burst start address. These inputs are ignored when device is deselected, i.e., NOP
(LD# = HIGH), or once BURST operation is in progress.
Synchronous Data IOs: Input data must meet setup and hold times around the rising
edges of K and K#. Output data is synchronized to the respective C and C# data
clocks or to K and K# if C and C# are tied to HIGH.
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be
defined. This definition includes address and read/write direction. All transactions
operate on a burst of 4 data (two clock periods of bus activity).
Synchronous Read/Write Input: When LD# is LOW, this input designates the access
type (READ when R, W# is HIGH, WRITE when R, W# is LOW) for the loaded
address. R, W# must meet the setup and hold times around the rising edge of K. If a
synchronous load command (LD# = LOW) is input, inputs of R, W# and LD# on the
subsequent rising edge of K are ignored.
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold
times around the rising edges of K and K# for each of the two rising edges comprising
the WRITE cycle. See
Pin Arrangement
for signal to data relationships.
See
Byte Write Operation
for relation between BWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising
edge of K, and registers data on the rising edge of K and the rising edge of K#. K# is
ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and
hold times around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output
data. The rising edge of C# is used as the output timing reference for first output data.
The rising edge of C is used as the output reference for second output data. Ideally,
C# is 180 degrees out of phase with C. When use of K and K# as the reference
instead of C and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed
unless C and C# are fixed to HIGH (i.e. toggle of C and C#)
DQ0 to DQ17
Input/Output
LD#
Input
R, W#
Input
BW0#, BW1#.
Input
K, K#
Input
C, C#
Input
R10DS0015EJ0200 Rev.2.00
October 6, 2011
Page 4 of 32
μ
PD44164184B
(2/2)
Symbol
CQ, CQ#
Type
Output
Description
Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched
to the synchronous data outputs and can be used as a data valid indication. These signals
run freely and do not stop when DQ tristates. If C and C# are stopped (if K and K# are
stopped in the single clock mode), CQ and CQ# will also stop.
Output Impedance Matching Input: This input is used to tune the device outputs to the
system data bus impedance. DQ, CQ and CQ# output impedance are set to 0.2 x RQ,
where RQ is a resistor from this bump to ground. The output impedance can be
minimized by directly connect ZQ to
V
DD
Q. This pin cannot be connected directly to GND
or left unconnected. The output impedance is adjusted every 20
μ
s upon power-up to
account for drifts in supply voltage and temperature. After replacement for a resistor, the
new output impedance is reset by implementing power-on sequence.
PLL Disable: When debugging the system or board, the operation can be performed at a
clock frequency slower than TKHKH (MAX.) without the PLL circuit being used, if DLL# =
LOW. The AC/DC characteristics cannot be guaranteed. For normal operation, DLL# must
be HIGH and it can be connected to
V
DD
Q through a 10 kΩ or less resistor.
IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the
JTAG function is not used in the circuit.
IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to V
SS
if the JTAG function
is not used in the circuit.
IEEE 1149.1 Test Output: 1.8 V I/O level.
When providing any external voltage to TDO signal, it is recommended to pull up to
V
DD
.
HSTL Input Reference Voltage: Nominally
V
DD
Q/2. Provides a reference voltage for the
input buffers.
Supply
Supply
Supply
Power Supply: 1.8 V nominal. See
Recommended DC Operating Conditions
and
DC
Characteristics
for range.
Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible.
See
Recommended DC Operating Conditions
and
DC Characteristics
for range.
Power Supply: Ground
No Connect: These signals are not connected internally.
ZQ
Input
DLL#
Input
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
Input
Input
Output
R10DS0015EJ0200 Rev.2.00
October 6, 2011
Page 5 of 32
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