K7N323631C
K7N321831C
1Mx36 & 2Mx18 Pipelined NtRAM
TM
36Mb NtRAM
TM
Specification
100TQFP/165FBGA with Pb / Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure couldresult in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 1.2 September 2008
K7N323631C
K7N321831C
Document Title
1Mx36 & 2Mx18-Bit Pipelined NtRAM
TM
1Mx36 & 2Mx18 Pipelined NtRAM
TM
Revision History
Rev. No.
0.0
0.1
0.2
0.3
1.0
1.1
1.2
History
1. Initial document.
1. Add the overshoot timing
1. Change ordering information
1. Change Samsung JEDEC Code in ID REGISTER DEFINITION
1. Finalize the datasheet
1. Correct typo
1. Correct typo
Draft Date
Jan. 2006
Feb. 2006
Apr. 2006
Jun. 2006
July. 2006
Aug. 2006
Sep. 2008
Remark
Advance
Preliminary
Preliminay
Preliminay
Final
Final
Final
-2-
Rev. 1.2 September 2008
K7N323631C
K7N321831C
36Mb NtRAM (Pipelined) Ordering Informa
tion
Org.
2Mx18
1Mx36
VDD (V)
3.3/2.5
3.3/2.5
3.3/2.5
3.3/2.5
Speed (ns)
4.0
6.0
4.0
6.0
1Mx36 & 2Mx18 Pipelined NtRAM
TM
Access Time (ns)
2.6
3.5
2.6
3.5
Part Number
K7N321831C-P(Q,E,F)
1
C(I)
2
25
K7N321831C-P(Q,E,F)
1
C(I)
2
16
K7N323631C-P(Q,E,F)
1
C(I)
2
25
K7N323631C-P(Q,E,F)
1
C(I)
2
16
RoHS Avail.
√
√
√
√
Note 1. P(Q,E,F) [Package type] : 100TQFP ; P-Pb Free, Q-Pb, 165FBGA ; E-Pb Free, F-Pb
2. C(I) [Operating Temperature] : C-Commercial, I-Industrial
-3-
Rev. 1.2 September 2008
K7N323631C
K7N321831C
1Mx36 & 2Mx18 Pipelined NtRAM
TM
1Mx36 & 2Mx18-Bit Pipelined NtRAM
TM
FEATURES
• V
DD
= 2.5 or 3.3V +/- 5% Power Supply.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data-
contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• 100-TQFP-1420A (Lead and Lead free package)
• 165FBGA(11x15 ball aray) with body size of 15mmx17mm.
(Lead and Lead free package)
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7N323631C and K7N321831C are 37,748,736-bits
Synchronous Static SRAMs.
The NtRAM
TM
, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N323631C and K7N321831C are implemented with
SAMSUNG′s high performance CMOS technology and is avail-
able in 100pin TQFP and 165FBGA packages. Multiple power
and ground pins minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
-25
4.0
2.6
2.6
-16
6.0
3.5
3.5
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
LBO
ADDRESS
REGISTER
A
2
~A
19
or A
2
~A
20
A
0
~A
1
BURST
ADDRESS
COUNTER
A′
0
~A′
1
1Mx36, 2Mx18
MEMORY
ARRAY
A [0:19]or
A [0:20]
CLK
CKE
K
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CONTROL
LOGIC
K
DATA-IN
REGISTER
DATA-IN
REGISTER
K
CS
1
CS
2
CS
2
ADV
WE
BW
x
(x=a,b,c,d or a,b)
OE
ZZ
DQa
0
~ DQd
7
or DQa
0
~ DQb
8
DQPa ~ DQPd
36 or 18
CONTROL
REGISTER
CONTROL
LOGIC
K
OUTPUT
REGISTER
BUFFER
NtRAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung.
-4-
Rev. 1.2 September 2008
K7N323631C
K7N321831C
PIN CONFIGURATION
(TOP VIEW)
BWd
BWb
BWa
BWc
1Mx36 & 2Mx18 Pipelined NtRAM
TM
CKE
ADV
CLK
CS
1
CS
2
CS
2
V
DD
V
SS
WE
A
18
A
17
83
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
V
DD
A
5
A
4
A
3
A
2
A
1
A
0
A
19
A
10
A
12
A
13
A
14
A
15
N.C.
N.C.
N.C.
LBO
V
SS
PIN NAME
SYMBOL
A
0
- A
19
PIN NAME
Address Inputs
TQFP PIN NO.
32,33,34,35,36,37,43,
44,45,46,47,48,49,50,
81,82,83,84,99,100
85
88
89
87
98
97
92
93,94,95,96
86
64
31
SYMBOL
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
DQPa~P
d
V
DDQ
V
SSQ
PIN NAME
TQFP PIN NO.
Power Supply(+3.3V) 14,15,16,41,65,66,91
Ground
17,40,67,90
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
38,39,42
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BWx(x=a,b,c,d)
OE
ZZ
LBO
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
Output Power Supply 4,11,20,27,54,61,70,77
(3.3V or 2.5V)
Output Ground
5,10,21,26,55,60,71,76
Note :
1. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-5-
Rev. 1.2 September 2008
A
16
A
11
50
DQPc
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
V
DD
V
DD
V
DD
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
DQPd
81
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7N323631C (1Mx36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
V
DD
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa
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